[PATCH] D83566: [ARM] CSEL generation

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: simon_tatham, efriedma, SjoerdMeijer, samparker, ostannard.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.

This adds a peephole optimisation to turn a t2MOVccr that could not be folded into any other instruction into a CSEL on 8.1-m. The t2MOVccr would usually be expanded into a conditional mov, that becomes an IT; MOV pair. We can instead generate a CSEL instruction, which can potentially be smaller and allows better register allocation freedom, which can help reduce codesize. Performance is more variable and may depend on the micrarchitecture details, but initial results look good. If we need to control this per-cpu, we can add a subtarget feature as we need it.

Original patch by David Penry.


https://reviews.llvm.org/D83566

Files:
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
  llvm/lib/Target/ARM/Thumb2InstrInfo.h
  llvm/test/CodeGen/Thumb2/csel.ll
  llvm/test/CodeGen/Thumb2/float-ops.ll
  llvm/test/CodeGen/Thumb2/mve-abs.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
  llvm/test/CodeGen/Thumb2/mve-vmaxv.ll

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