[PATCH] D81172: [AMDGPU] Implement hardware bug workaround for image instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:3221-3222
+
+  if (ImageStore && ST.hasImageStoreD16Bug())
+  {
+    SmallVector<Register, 4> PackedRegs;
----------------
Brace formatting


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:3226-3228
+      // TODO Handle v3f16
+      if (StoreVT.getNumElements() == 3)
+        return Reg;
----------------
There's no obstacle to handling v3 here, it should work in the other cases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81172/new/

https://reviews.llvm.org/D81172