[PATCH] D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions

[Paolo Savini via Phabricator via llvm-commits]

PaoloS marked 2 inline comments as done.
PaoloS added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:173
+
+bool RISCVDAGToDAGISel::SelectSLOI(SDValue N, SDValue &RS1, SDValue &Shamt) {
+  MVT XLenVT = Subtarget->getXLenVT();
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lewis-revill wrote:
> Indentation within these Select functions is messed up, presumably due to a mix of tabs and spaces.
Yes, I was trying to use spaces only in the end. Must have missed these.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:262
+bool RISCVDAGToDAGISel::SelectSLOIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
+  if (N.getOpcode() == ISD::SIGN_EXTEND_INREG &&
+      cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) {
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lewis-revill wrote:
> I'm not sure the convention other select functions for W instructions follow but perhaps an assert for IsRV64 should be added for completeness?
Well, SLOIW exists only on RV64. I could add it, but I think it would be a bit redundant if I guard the selects only for RV64.
But yes, for completeness I probably should.


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  https://reviews.llvm.org/D79870/new/

https://reviews.llvm.org/D79870