[PATCH] D79874: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:666
+let Predicates = [HasStdExtZbs, IsRV64] in
+def : Pat<(and (xor (riscv_sllw 1, GPR:$rs2), -1), GPR:$rs1),
+          (SBCLR GPR:$rs1, GPR:$rs2)>;
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Why does this need to be `riscv_sllw` as opposed to `shl`? Isn't the former intended for matching patterns resulting from a 32 bit operation?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79874/new/

https://reviews.llvm.org/D79874