[PATCH] D81647: MIR Statepoint refactoring. Part 3: Spill GC Ptr regs.

[Denis Antrushin via Phabricator via llvm-commits]

dantrushin updated this revision to Diff 276470.
dantrushin added a comment.

Add (hand crafted) test for shared landing pad;
Slightly change cache handling code to better handle shared landing pads;
Improve debug output;


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81647/new/

https://reviews.llvm.org/D81647

Files:
  llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
  llvm/test/CodeGen/X86/statepoint-fixup-call.mir
  llvm/test/CodeGen/X86/statepoint-fixup-invoke.mir
  llvm/test/CodeGen/X86/statepoint-fixup-shared-ehpad.mir
  llvm/test/CodeGen/X86/statepoint-vreg.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D81647.276470.patch
Type: text/x-patch
Size: 41533 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200708/b709ede1/attachment.bin>