[llvm] cca8578 - [SystemZ] Allow specifying integer registers as part of the address calculation
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 8 09:20:52 PDT 2020
Author: Ulrich Weigand
Date: 2020-07-08T18:20:24+02:00
New Revision: cca8578efab096fddcb0134b28b17f4758e9afa0
URL: https://github.com/llvm/llvm-project/commit/cca8578efab096fddcb0134b28b17f4758e9afa0
DIFF: https://github.com/llvm/llvm-project/commit/cca8578efab096fddcb0134b28b17f4758e9afa0.diff
LOG: [SystemZ] Allow specifying integer registers as part of the address calculation
Revision e1de2773a534957305d7a559c6d88c4b5ac354e2 provided support for
accepting integer registers in inline asm i.e.
__asm("lhi %r0, 5") -> lhi %r0, 5
__asm("lhi 0, 5") -> lhi 0,5
This patch aims to extend this support to instructions which compute
addresses as well. (i.e instructions of type BDMem and BD[X|R|V|L]Mem)
Author: anirudhp
Differential Revision: https://reviews.llvm.org/D83251
Added:
Modified:
llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
llvm/test/MC/SystemZ/insn-bad.s
llvm/test/MC/SystemZ/insn-good-z13.s
llvm/test/MC/SystemZ/insn-good-z14.s
llvm/test/MC/SystemZ/insn-good-z15.s
llvm/test/MC/SystemZ/insn-good.s
llvm/test/MC/SystemZ/regs-good.s
llvm/test/MC/SystemZ/tokens.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index a3110248e8e0..d5a3a19446c7 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -405,14 +405,16 @@ class SystemZAsmParser : public MCTargetAsmParser {
bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
+ bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
+
OperandMatchResultTy parseRegister(OperandVector &Operands,
RegisterKind Kind);
OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
- bool parseAddress(bool &HaveReg1, Register &Reg1,
- bool &HaveReg2, Register &Reg2,
- const MCExpr *&Disp, const MCExpr *&Length);
+ bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
+ Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
+ bool HasLength = false, bool HasVectorIndex = false);
bool parseAddressRegister(Register &Reg);
bool ParseDirectiveInsn(SMLoc L);
@@ -748,82 +750,60 @@ bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
// Parse a register of kind Kind and add it to Operands.
OperandMatchResultTy
SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
- SMLoc StartLoc, EndLoc;
- unsigned RegNum;
+ Register Reg;
+ RegisterGroup Group;
+ switch (Kind) {
+ case GR32Reg:
+ case GRH32Reg:
+ case GR64Reg:
+ case GR128Reg:
+ Group = RegGR;
+ break;
+ case FP32Reg:
+ case FP64Reg:
+ case FP128Reg:
+ Group = RegFP;
+ break;
+ case VR32Reg:
+ case VR64Reg:
+ case VR128Reg:
+ Group = RegV;
+ break;
+ case AR32Reg:
+ Group = RegAR;
+ break;
+ case CR64Reg:
+ Group = RegCR;
+ break;
+ }
- // Handle register names of the form %<prefix><number>.
+ // Handle register names of the form %<prefix><number>
if (Parser.getTok().is(AsmToken::Percent)) {
- Register Reg;
if (parseRegister(Reg))
return MatchOperand_ParseFail;
- // Verify that a register prefix appropriate for Kind was used.
- bool PrefixMatch;
- switch (Kind) {
- case GR32Reg:
- case GRH32Reg:
- case GR64Reg:
- case GR128Reg:
- PrefixMatch = Reg.Group == RegGR;
- break;
- case FP32Reg:
- case FP64Reg:
- case FP128Reg:
- PrefixMatch = Reg.Group == RegFP;
- break;
- case VR32Reg:
- case VR64Reg:
- case VR128Reg:
- // It is OK to use the %f prefix with vector instructions that
- // expect some VR..Reg kind, so accept the RegFP group as well.
- PrefixMatch = Reg.Group == RegV || Reg.Group == RegFP;
- break;
- case AR32Reg:
- PrefixMatch = Reg.Group == RegAR;
- break;
- case CR64Reg:
- PrefixMatch = Reg.Group == RegCR;
- break;
- }
- if (!PrefixMatch) {
- Error(Reg.StartLoc, "invalid operand for instruction");
- return MatchOperand_ParseFail;
- }
-
- RegNum = Reg.Num;
- StartLoc = Reg.StartLoc;
- EndLoc = Reg.EndLoc;
- }
- // Also allow specifying just a plain register number as integer.
- else if (Parser.getTok().is(AsmToken::Integer)) {
- const MCExpr *Register;
- StartLoc = Parser.getTok().getLoc();
- if (Parser.parseExpression(Register))
- return MatchOperand_ParseFail;
-
- auto *CE = dyn_cast<MCConstantExpr>(Register);
- if (!CE)
- return MatchOperand_ParseFail;
-
- int64_t MaxRegNum;
- switch (Kind) {
- case VR32Reg:
- case VR64Reg:
- case VR128Reg:
- MaxRegNum = 31;
+ // Check the parsed register group "Reg.Group" with the expected "Group"
+ // Have to error out if user specified wrong prefix.
+ switch (Group) {
+ case RegGR:
+ case RegFP:
+ case RegAR:
+ case RegCR:
+ if (Group != Reg.Group) {
+ Error(Reg.StartLoc, "invalid operand for instruction");
+ return MatchOperand_ParseFail;
+ }
break;
- default:
- MaxRegNum = 15;
+ case RegV:
+ if (Reg.Group != RegV && Reg.Group != RegFP) {
+ Error(Reg.StartLoc, "invalid operand for instruction");
+ return MatchOperand_ParseFail;
+ }
break;
}
- int64_t Value = CE->getValue();
- if (Value < 0 || Value > MaxRegNum) {
- Error(StartLoc, "invalid register");
+ } else if (Parser.getTok().is(AsmToken::Integer)) {
+ if (parseIntegerRegister(Reg, Group))
return MatchOperand_ParseFail;
- }
- RegNum = (unsigned) Value;
-
- EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
}
// Otherwise we didn't match a register operand.
else
@@ -845,13 +825,13 @@ SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
case AR32Reg: Regs = SystemZMC::AR32Regs; break;
case CR64Reg: Regs = SystemZMC::CR64Regs; break;
}
- if (Regs[RegNum] == 0) {
- Error(StartLoc, "invalid register pair");
+ if (Regs[Reg.Num] == 0) {
+ Error(Reg.StartLoc, "invalid register pair");
return MatchOperand_ParseFail;
}
- Operands.push_back(SystemZOperand::createReg(Kind, Regs[RegNum],
- StartLoc, EndLoc));
+ Operands.push_back(
+ SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
return MatchOperand_Success;
}
@@ -916,11 +896,39 @@ SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
return MatchOperand_Success;
}
+bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
+ RegisterGroup Group) {
+ Reg.StartLoc = Parser.getTok().getLoc();
+ // We have an integer token
+ const MCExpr *Register;
+ if (Parser.parseExpression(Register))
+ return true;
+
+ const auto *CE = dyn_cast<MCConstantExpr>(Register);
+ if (!CE)
+ return true;
+
+ int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
+ int64_t Value = CE->getValue();
+ if (Value < 0 || Value > MaxRegNum) {
+ Error(Parser.getTok().getLoc(), "invalid register");
+ return true;
+ }
+
+ // Assign the Register Number
+ Reg.Num = (unsigned)Value;
+ Reg.Group = Group;
+ Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
+
+ // At this point, successfully parsed an integer register.
+ return false;
+}
+
// Parse a memory operand into Reg1, Reg2, Disp, and Length.
bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
bool &HaveReg2, Register &Reg2,
- const MCExpr *&Disp,
- const MCExpr *&Length) {
+ const MCExpr *&Disp, const MCExpr *&Length,
+ bool HasLength, bool HasVectorIndex) {
// Parse the displacement, which must always be present.
if (getParser().parseExpression(Disp))
return true;
@@ -929,6 +937,27 @@ bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
HaveReg1 = false;
HaveReg2 = false;
Length = nullptr;
+
+ // If we have a scenario as below:
+ // vgef %v0, 0(0), 0
+ // This is an example of a "BDVMem" instruction type.
+ //
+ // So when we parse this as an integer register, the register group
+ // needs to be tied to "RegV". Usually when the prefix is passed in
+ // as %<prefix><reg-number> its easy to check which group it should belong to
+ // However, if we're passing in just the integer there's no real way to
+ // "check" what register group it should belong to.
+ //
+ // When the user passes in the register as an integer, the user assumes that
+ // the compiler is responsible for substituting it as the right kind of
+ // register. Whereas, when the user specifies a "prefix", the onus is on
+ // the user to make sure they pass in the right kind of register.
+ //
+ // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
+ // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
+ // (i.e. insn is of type BDVMem) is true.
+ RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
+
if (getLexer().is(AsmToken::LParen)) {
Parser.Lex();
@@ -937,18 +966,47 @@ bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
HaveReg1 = true;
if (parseRegister(Reg1))
return true;
+ }
+ // So if we have an integer as the first token in ([tok1], ..), it could:
+ // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
+ // instructions)
+ // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
+ else if (getLexer().is(AsmToken::Integer)) {
+ if (HasLength) {
+ // Instruction has a "Length" field, safe to parse the first token as
+ // the "Length" field
+ if (getParser().parseExpression(Length))
+ return true;
+ } else {
+ // Otherwise, if the instruction has no "Length" field, parse the
+ // token as a "Register". We don't have to worry about whether the
+ // instruction is invalid here, because the caller will take care of
+ // error reporting.
+ HaveReg1 = true;
+ if (parseIntegerRegister(Reg1, RegGroup))
+ return true;
+ }
} else {
- // Parse the length.
- if (getParser().parseExpression(Length))
- return true;
+ // If its not an integer or a percent token, then if the instruction
+ // is reported to have a "Length" then, parse it as "Length".
+ if (HasLength) {
+ if (getParser().parseExpression(Length))
+ return true;
+ }
}
// Check whether there's a second register.
if (getLexer().is(AsmToken::Comma)) {
Parser.Lex();
HaveReg2 = true;
- if (parseRegister(Reg2))
- return true;
+
+ if (getLexer().is(AsmToken::Integer)) {
+ if (parseIntegerRegister(Reg2, RegGR))
+ return true;
+ } else {
+ if (parseRegister(Reg2))
+ return true;
+ }
}
// Consume the closing bracket.
@@ -983,7 +1041,11 @@ SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
bool HaveReg1, HaveReg2;
const MCExpr *Disp;
const MCExpr *Length;
- if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
+
+ bool HasLength = (MemKind == BDLMem) ? true : false;
+ bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
+ if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
+ HasVectorIndex))
return MatchOperand_ParseFail;
const unsigned *Regs;
@@ -1001,11 +1063,7 @@ SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
return MatchOperand_ParseFail;
Base = Regs[Reg1.Num];
}
- // There must be no Reg2 or length.
- if (Length) {
- Error(StartLoc, "invalid use of length addressing");
- return MatchOperand_ParseFail;
- }
+ // There must be no Reg2.
if (HaveReg2) {
Error(StartLoc, "invalid use of indexed addressing");
return MatchOperand_ParseFail;
@@ -1029,11 +1087,6 @@ SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
return MatchOperand_ParseFail;
Base = Regs[Reg2.Num];
}
- // There must be no length.
- if (Length) {
- Error(StartLoc, "invalid use of length addressing");
- return MatchOperand_ParseFail;
- }
break;
case BDLMem:
// If we have Reg2, it must be an address register.
@@ -1066,11 +1119,6 @@ SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
return MatchOperand_ParseFail;
Base = Regs[Reg2.Num];
}
- // There must be no length.
- if (Length) {
- Error(StartLoc, "invalid use of length addressing");
- return MatchOperand_ParseFail;
- }
break;
case BDVMem:
// We must have Reg1, and it must be a vector register.
@@ -1085,16 +1133,11 @@ SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
return MatchOperand_ParseFail;
Base = Regs[Reg2.Num];
}
- // There must be no length.
- if (Length) {
- Error(StartLoc, "invalid use of length addressing");
- return MatchOperand_ParseFail;
- }
break;
}
SMLoc EndLoc =
- SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
+ SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
Index, Length, LengthReg,
StartLoc, EndLoc));
@@ -1323,7 +1366,8 @@ bool SystemZAsmParser::parseOperand(OperandVector &Operands,
bool HaveReg1, HaveReg2;
const MCExpr *Expr;
const MCExpr *Length;
- if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
+ if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
+ /*HasLength*/ true, /*HasVectorIndex*/ true))
return true;
// If the register combination is not valid for any instruction, reject it.
// Otherwise, fall back to reporting an unrecognized instruction.
diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s
index c330fa496a25..59174067c4b2 100644
--- a/llvm/test/MC/SystemZ/insn-bad.s
+++ b/llvm/test/MC/SystemZ/insn-bad.s
@@ -1343,7 +1343,7 @@
#CHECK: clc 0, 0
#CHECK: error: missing length in address
#CHECK: clc 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: clc 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: clc 0(0,%r1), 0(%r1)
@@ -2573,7 +2573,7 @@
#CHECK: ed 0, 0
#CHECK: error: missing length in address
#CHECK: ed 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: ed 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: ed 0(0,%r1), 0(%r1)
@@ -2611,7 +2611,7 @@
#CHECK: edmk 0, 0
#CHECK: error: missing length in address
#CHECK: edmk 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: edmk 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: edmk 0(0,%r1), 0(%r1)
@@ -4373,7 +4373,7 @@
#CHECK: mvc 0, 0
#CHECK: error: missing length in address
#CHECK: mvc 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: mvc 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: mvc 0(0,%r1), 0(%r1)
@@ -4428,7 +4428,7 @@
#CHECK: mvcin 0, 0
#CHECK: error: missing length in address
#CHECK: mvcin 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: mvcin 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: mvcin 0(0,%r1), 0(%r1)
@@ -4462,7 +4462,7 @@
mvcin 0(1,%r2), 0(%r1,%r2)
mvcin 0(-), 0
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: mvck 0(%r1,%r1), 0(2,%r1), %r3
#CHECK: error: invalid operand
#CHECK: mvck -1(%r1,%r1), 0(%r1), %r3
@@ -4474,7 +4474,7 @@
#CHECK: mvck 0(%r1,%r1), 4096(%r1), %r3
#CHECK: error: invalid use of indexed addressing
#CHECK: mvck 0(%r1,%r2), 0(%r1,%r2), %r3
-#CHECK: error: unknown token in expression
+#CHECK: error: unexpected token in address
#CHECK: mvck 0(-), 0, %r3
mvck 0(%r1,%r1), 0(2,%r1), %r3
@@ -4538,7 +4538,7 @@
mvcos 0(%r1), -1(%r15), %r2
mvcos 0(%r1), 4096(%r15), %r2
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: mvcp 0(%r1,%r1), 0(2,%r1), %r3
#CHECK: error: invalid operand
#CHECK: mvcp -1(%r1,%r1), 0(%r1), %r3
@@ -4550,7 +4550,7 @@
#CHECK: mvcp 0(%r1,%r1), 4096(%r1), %r3
#CHECK: error: invalid use of indexed addressing
#CHECK: mvcp 0(%r1,%r2), 0(%r1,%r2), %r3
-#CHECK: error: unknown token in expression
+#CHECK: error: unexpected token in address
#CHECK: mvcp 0(-), 0, %r3
mvcp 0(%r1,%r1), 0(2,%r1), %r3
@@ -4561,7 +4561,7 @@
mvcp 0(%r1,%r2), 0(%r1,%r2), %r3
mvcp 0(-), 0, %r3
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: mvcs 0(%r1,%r1), 0(2,%r1), %r3
#CHECK: error: invalid operand
#CHECK: mvcs -1(%r1,%r1), 0(%r1), %r3
@@ -4573,7 +4573,7 @@
#CHECK: mvcs 0(%r1,%r1), 4096(%r1), %r3
#CHECK: error: invalid use of indexed addressing
#CHECK: mvcs 0(%r1,%r2), 0(%r1,%r2), %r3
-#CHECK: error: unknown token in expression
+#CHECK: error: unexpected token in address
#CHECK: mvcs 0(-), 0, %r3
mvcs 0(%r1,%r1), 0(2,%r1), %r3
@@ -4690,7 +4690,7 @@
#CHECK: mvn 0, 0
#CHECK: error: missing length in address
#CHECK: mvn 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: mvn 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: mvn 0(0,%r1), 0(%r1)
@@ -4775,7 +4775,7 @@
#CHECK: mvz 0, 0
#CHECK: error: missing length in address
#CHECK: mvz 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: mvz 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: mvz 0(0,%r1), 0(%r1)
@@ -4917,7 +4917,7 @@
#CHECK: nc 0, 0
#CHECK: error: missing length in address
#CHECK: nc 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: nc 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: nc 0(0,%r1), 0(%r1)
@@ -5071,7 +5071,7 @@
#CHECK: oc 0, 0
#CHECK: error: missing length in address
#CHECK: oc 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: oc 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: oc 0(0,%r1), 0(%r1)
@@ -5319,7 +5319,7 @@
#CHECK: pka 0, 0
#CHECK: error: missing length in address
#CHECK: pka 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: pka 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: pka 0(%r1), 0(0,%r1)
@@ -5357,7 +5357,7 @@
#CHECK: pku 0, 0
#CHECK: error: missing length in address
#CHECK: pku 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: pku 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: pku 0(%r1), 0(0,%r1)
@@ -6232,7 +6232,7 @@
#CHECK: srp 0, 0, 0
#CHECK: error: missing length in address
#CHECK: srp 0(%r1), 0(%r1), 0
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: srp 0(1,%r1), 0(2,%r1), 0
#CHECK: error: invalid operand
#CHECK: srp 0(0,%r1), 0(%r1), 0
@@ -7118,7 +7118,7 @@
#CHECK: tr 0, 0
#CHECK: error: missing length in address
#CHECK: tr 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: tr 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: tr 0(0,%r1), 0(%r1)
@@ -7216,7 +7216,7 @@
#CHECK: trt 0, 0
#CHECK: error: missing length in address
#CHECK: trt 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: trt 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: trt 0(0,%r1), 0(%r1)
@@ -7276,7 +7276,7 @@
#CHECK: trtr 0, 0
#CHECK: error: missing length in address
#CHECK: trtr 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: trtr 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: trtr 0(0,%r1), 0(%r1)
@@ -7405,7 +7405,7 @@
#CHECK: unpka 0, 0
#CHECK: error: missing length in address
#CHECK: unpka 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: unpka 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: unpka 0(0,%r1), 0(%r1)
@@ -7443,7 +7443,7 @@
#CHECK: unpku 0, 0
#CHECK: error: missing length in address
#CHECK: unpku 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: unpku 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: unpku 0(0,%r1), 0(%r1)
@@ -7489,7 +7489,7 @@
#CHECK: xc 0, 0
#CHECK: error: missing length in address
#CHECK: xc 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
#CHECK: xc 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: xc 0(0,%r1), 0(%r1)
diff --git a/llvm/test/MC/SystemZ/insn-good-z13.s b/llvm/test/MC/SystemZ/insn-good-z13.s
index df99a1f48951..4e3ba50ad7f9 100644
--- a/llvm/test/MC/SystemZ/insn-good-z13.s
+++ b/llvm/test/MC/SystemZ/insn-good-z13.s
@@ -2879,6 +2879,20 @@
vgbm %v31, 0
vgbm %v17, 0x1234
+#CHECK: vgef %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
+#CHECK: vgef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
+#CHECK: vgef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
+#CHECK: vgef %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13]
+#CHECK: vgef %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x13]
+#CHECK: vgef %v0, 0(%v31,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x13]
+#CHECK: vgef %v0, 4095(%v0,%r1), 0 # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x13]
+#CHECK: vgef %v15, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x13]
+#CHECK: vgef %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x13]
+#CHECK: vgef %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x13]
+#CHECK: vgef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
+#CHECK: vgef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
+#CHECK: vgef %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13]
+#CHECK: vgef %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x13]
#CHECK: vgef %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
#CHECK: vgef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
#CHECK: vgef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
@@ -2900,7 +2914,35 @@
vgef %v15, 0(%v0,%r1), 0
vgef %v31, 0(%v0,%r1), 0
vgef %v10, 1000(%v19,%r7), 1
+ vgef %v0, 0(0,%r1), 0
+ vgef %v0, 0(%v0,1), 3
+ vgef %v0, 0(0,%r15), 0
+ vgef %v0, 0(%v15,1), 0
+ vgef 0, 0(0), 0
+ vgef 0, 0(0,1), 0
+ vgef 0, 0(0,1), 3
+ vgef 0, 0(0,15), 0
+ vgef 0, 0(15,1), 0
+ vgef 0, 0(31,1), 0
+ vgef 0, 4095(0, 1), 0
+ vgef 15, 0(0,1), 0
+ vgef 31, 0(0,1), 0
+ vgef 10, 1000(19,7), 1
+#CHECK: vgeg %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
+#CHECK: vgeg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
+#CHECK: vgeg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
+#CHECK: vgeg %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12]
+#CHECK: vgeg %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x12]
+#CHECK: vgeg %v0, 0(%v31,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x12]
+#CHECK: vgeg %v0, 4095(%v0,%r1), 0 # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x12]
+#CHECK: vgeg %v15, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x12]
+#CHECK: vgeg %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x12]
+#CHECK: vgeg %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x12]
+#CHECK: vgeg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
+#CHECK: vgeg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
+#CHECK: vgeg %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12]
+#CHECK: vgeg %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x12]
#CHECK: vgeg %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
#CHECK: vgeg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
#CHECK: vgeg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
@@ -2922,6 +2964,21 @@
vgeg %v15, 0(%v0,%r1), 0
vgeg %v31, 0(%v0,%r1), 0
vgeg %v10, 1000(%v19,%r7), 1
+ vgeg %v0, 0(0,%r1), 0
+ vgeg %v0, 0(%v0,1), 1
+ vgeg %v0, 0(0,%r15), 0
+ vgeg %v0, 0(%v15,1), 0
+ vgeg 0, 0(0), 0
+ vgeg 0, 0(0,1), 0
+ vgeg 0, 0(0,1), 1
+ vgeg 0, 0(0,15), 0
+ vgeg 0, 0(15,1), 0
+ vgeg 0, 0(31,1), 0
+ vgeg 0, 4095(0,1), 0
+ vgeg 15, 0(0,1), 0
+ vgeg 31, 0(0,1), 0
+ vgeg 10, 1000(19,7), 1
+
#CHECK: vgfm %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xb4]
#CHECK: vgfm %v0, %v0, %v0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xb4]
@@ -3229,6 +3286,16 @@
vl %v31, 0
vl %v18, 0x567(%r3,%r4), 3
+#CHECK: vlbb %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x07]
+#CHECK: vlbb %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x07]
+#CHECK: vlbb %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x07]
+#CHECK: vlbb %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x07]
+#CHECK: vlbb %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x07]
+#CHECK: vlbb %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x07]
+#CHECK: vlbb %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x07]
+#CHECK: vlbb %v18, 1383(%r3,%r4), 8 # encoding: [0xe7,0x23,0x45,0x67,0x88,0x07]
+#CHECK: vlbb %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x07]
+#CHECK: vlbb %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x07]
#CHECK: vlbb %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x07]
#CHECK: vlbb %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x07]
#CHECK: vlbb %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x07]
@@ -3246,6 +3313,17 @@
vlbb %v15, 0, 0
vlbb %v31, 0, 0
vlbb %v18, 1383(%r3,%r4), 8
+ vlbb %v18, 1383(%r3, 4), 8
+ vlbb %v0, 0(15,%r1), 0
+ vlbb %v0, 0(%r15,1), 0
+ vlbb 0, 0, 0
+ vlbb 0, 0, 15
+ vlbb 0, 4095, 0
+ vlbb 0, 0(15), 0
+ vlbb 0, 0(15,1), 0
+ vlbb 15, 0, 0
+ vlbb 31, 0, 0
+ vlbb 18, 1383(3,4), 8
#CHECK: vlc %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xde]
#CHECK: vlc %v0, %v0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xde]
@@ -3922,6 +4000,7 @@
#CHECK: vlvgf %v0, %r0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x22]
#CHECK: vlvgf %v0, %r0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x22]
#CHECK: vlvgf %v0, %r0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x22]
+#CHECK: vlvgf %v0, %r0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x22]
#CHECK: vlvgf %v0, %r15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x22]
#CHECK: vlvgf %v15, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x22]
#CHECK: vlvgf %v31, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x22]
@@ -3930,6 +4009,7 @@
vlvgf %v0, %r0, 0
vlvgf %v0, %r0, 4095
vlvgf %v0, %r0, 0(%r15)
+ vlvgf %v0, %r0, 0(15)
vlvgf %v0, %r15, 0
vlvgf %v15, %r0, 0
vlvgf %v31, %r0, 0
diff --git a/llvm/test/MC/SystemZ/insn-good-z14.s b/llvm/test/MC/SystemZ/insn-good-z14.s
index 1fcdcb4ccab0..ec12283ecbae 100644
--- a/llvm/test/MC/SystemZ/insn-good-z14.s
+++ b/llvm/test/MC/SystemZ/insn-good-z14.s
@@ -4,6 +4,16 @@
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch12 -show-encoding %s \
# RUN: | FileCheck %s
+#CHECK: agh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x38]
+#CHECK: agh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x38]
+#CHECK: agh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x38]
+#CHECK: agh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x38]
+#CHECK: agh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x38]
+#CHECK: agh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x38]
+#CHECK: agh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x38]
+#CHECK: agh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x38]
+#CHECK: agh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x38]
+#CHECK: agh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x38]
#CHECK: agh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x38]
#CHECK: agh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x38]
#CHECK: agh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x38]
@@ -25,6 +35,16 @@
agh %r0, 524287(%r1,%r15)
agh %r0, 524287(%r15,%r1)
agh %r15, 0
+ agh 0, -524288
+ agh 0, -1
+ agh 0, 0
+ agh 0, 1
+ agh 0, 524287
+ agh 0, 0(1)
+ agh 0, 0(15)
+ agh 0, 524287(1,15)
+ agh 0, 524287(15,1)
+ agh 15, 0
#CHECK: bi -524288 # encoding: [0xe3,0xf0,0x00,0x00,0x80,0x47]
#CHECK: bi -1 # encoding: [0xe3,0xf0,0x0f,0xff,0xff,0x47]
@@ -1200,6 +1220,13 @@
vlip %v31, 0, 0
vlip %v17, 0x1234, 7
+#CHECK: vllezlf %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x60,0x04]
+#CHECK: vllezlf %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x60,0x04]
+#CHECK: vllezlf %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x60,0x04]
+#CHECK: vllezlf %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x60,0x04]
+#CHECK: vllezlf %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x60,0x04]
+#CHECK: vllezlf %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x68,0x04]
+#CHECK: vllezlf %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x68,0x04]
#CHECK: vllezlf %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x60,0x04]
#CHECK: vllezlf %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x60,0x04]
#CHECK: vllezlf %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x60,0x04]
@@ -1215,7 +1242,21 @@
vllezlf %v15, 0
vllezlf %v31, 0
vllezlf %v18, 0x567(%r3,%r4)
+ vllezlf 0, 0
+ vllezlf 0, 4095
+ vllezlf 0, 0(15)
+ vllezlf 0, 0(15,1)
+ vllezlf 15, 0
+ vllezlf 31, 0
+ vllezlf 18, 0x567(3,4)
+#CHECK: vlrl %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x35]
+#CHECK: vlrl %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x35]
+#CHECK: vlrl %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x35]
+#CHECK: vlrl %v0, 0, 255 # encoding: [0xe6,0xff,0x00,0x00,0x00,0x35]
+#CHECK: vlrl %v15, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x35]
+#CHECK: vlrl %v31, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x35]
+#CHECK: vlrl %v18, 1383(%r4), 3 # encoding: [0xe6,0x03,0x45,0x67,0x21,0x35]
#CHECK: vlrl %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x35]
#CHECK: vlrl %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x35]
#CHECK: vlrl %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x35]
@@ -1231,6 +1272,13 @@
vlrl %v15, 0, 0
vlrl %v31, 0, 0
vlrl %v18, 1383(%r4), 3
+ vlrl 0, 0, 0
+ vlrl 0, 4095, 0
+ vlrl 0, 0(15), 0
+ vlrl 0, 0, 255
+ vlrl 15, 0, 0
+ vlrl 31, 0, 0
+ vlrl 18, 1383(4), 3
#CHECK: vlrlr %v0, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x37]
#CHECK: vlrlr %v0, %r0, 4095 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x37]
diff --git a/llvm/test/MC/SystemZ/insn-good-z15.s b/llvm/test/MC/SystemZ/insn-good-z15.s
index 1eb3b743cc61..36476161ea46 100644
--- a/llvm/test/MC/SystemZ/insn-good-z15.s
+++ b/llvm/test/MC/SystemZ/insn-good-z15.s
@@ -24,6 +24,13 @@
kdsa %r15, %r2
kdsa %r7, %r10
+#CHECK: vllebrzg %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x30,0x04]
+#CHECK: vllebrzg %v0, 4095 # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x04]
+#CHECK: vllebrzg %v0, 0(%r15) # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x04]
+#CHECK: vllebrzg %v0, 0(%r15,%r1) # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x04]
+#CHECK: vllebrzg %v15, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x04]
+#CHECK: vllebrzg %v31, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x04]
+#CHECK: vllebrzg %v18, 1383(%r3,%r4) # encoding: [0xe6,0x23,0x45,0x67,0x38,0x04]
#CHECK: vllebrzg %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x30,0x04]
#CHECK: vllebrzg %v0, 4095 # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x04]
#CHECK: vllebrzg %v0, 0(%r15) # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x04]
@@ -39,6 +46,14 @@
ldrv %f15, 0
ldrv %v31, 0
ldrv %v18, 0x567(%r3,%r4)
+ ldrv 0, 0
+ ldrv 0, 4095
+ ldrv 0, 0(15)
+ ldrv 0, 0(15,1)
+ ldrv 15, 0
+ ldrv 31, 0
+ ldrv 18, 0x567(3,4)
+
#CHECK: vllebrze %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x60,0x04]
#CHECK: vllebrze %v0, 4095 # encoding: [0xe6,0x00,0x0f,0xff,0x60,0x04]
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 3c5b34abe0a9..07f721bfa5e4 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -1,6 +1,13 @@
# For z10 and above.
# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s
+#CHECK: a %r0, 0 # encoding: [0x5a,0x00,0x00,0x00]
+#CHECK: a %r0, 4095 # encoding: [0x5a,0x00,0x0f,0xff]
+#CHECK: a %r0, 0(%r1) # encoding: [0x5a,0x00,0x10,0x00]
+#CHECK: a %r0, 0(%r15) # encoding: [0x5a,0x00,0xf0,0x00]
+#CHECK: a %r0, 4095(%r1,%r15) # encoding: [0x5a,0x01,0xff,0xff]
+#CHECK: a %r0, 4095(%r15,%r1) # encoding: [0x5a,0x0f,0x1f,0xff]
+#CHECK: a %r15, 0 # encoding: [0x5a,0xf0,0x00,0x00]
#CHECK: a %r0, 0 # encoding: [0x5a,0x00,0x00,0x00]
#CHECK: a %r0, 4095 # encoding: [0x5a,0x00,0x0f,0xff]
#CHECK: a %r0, 0(%r1) # encoding: [0x5a,0x00,0x10,0x00]
@@ -16,6 +23,14 @@
a %r0, 4095(%r1,%r15)
a %r0, 4095(%r15,%r1)
a %r15, 0
+ a 0, 0
+ a 0, 4095
+ a 0, 0(1)
+ a 0, 0(15)
+ a 0, 4095(1,15)
+ a 0, 4095(15,1)
+ a 15, 0
+
#CHECK: ad %f0, 0 # encoding: [0x6a,0x00,0x00,0x00]
#CHECK: ad %f0, 4095 # encoding: [0x6a,0x00,0x0f,0xff]
@@ -319,6 +334,13 @@
ahy %r0, 524287(%r15,%r1)
ahy %r15, 0
+#CHECK: al %r0, 0 # encoding: [0x5e,0x00,0x00,0x00]
+#CHECK: al %r0, 4095 # encoding: [0x5e,0x00,0x0f,0xff]
+#CHECK: al %r0, 0(%r1) # encoding: [0x5e,0x00,0x10,0x00]
+#CHECK: al %r0, 0(%r15) # encoding: [0x5e,0x00,0xf0,0x00]
+#CHECK: al %r0, 4095(%r1,%r15) # encoding: [0x5e,0x01,0xff,0xff]
+#CHECK: al %r0, 4095(%r15,%r1) # encoding: [0x5e,0x0f,0x1f,0xff]
+#CHECK: al %r15, 0 # encoding: [0x5e,0xf0,0x00,0x00]
#CHECK: al %r0, 0 # encoding: [0x5e,0x00,0x00,0x00]
#CHECK: al %r0, 4095 # encoding: [0x5e,0x00,0x0f,0xff]
#CHECK: al %r0, 0(%r1) # encoding: [0x5e,0x00,0x10,0x00]
@@ -334,6 +356,13 @@
al %r0, 4095(%r1,%r15)
al %r0, 4095(%r15,%r1)
al %r15, 0
+ al 0, 0
+ al 0, 4095
+ al 0, 0(1)
+ al 0, 0(15)
+ al 0, 4095(1,15)
+ al 0, 4095(15,1)
+ al 15, 0
#CHECK: alc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x98]
#CHECK: alc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x98]
@@ -407,6 +436,16 @@
alfi %r0, (1 << 32) - 1
alfi %r15, 0
+#CHECK: alg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x0a]
+#CHECK: alg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x0a]
+#CHECK: alg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x0a]
+#CHECK: alg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x0a]
+#CHECK: alg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x0a]
+#CHECK: alg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x0a]
+#CHECK: alg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x0a]
+#CHECK: alg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x0a]
+#CHECK: alg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x0a]
+#CHECK: alg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x0a]
#CHECK: alg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x0a]
#CHECK: alg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x0a]
#CHECK: alg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x0a]
@@ -428,6 +467,16 @@
alg %r0, 524287(%r1,%r15)
alg %r0, 524287(%r15,%r1)
alg %r15, 0
+ alg 0, -524288
+ alg 0, -1
+ alg 0, 0
+ alg 0, 1
+ alg 0, 524287
+ alg 0, 0(1)
+ alg 0, 0(15)
+ alg 0, 524287(1,15)
+ alg 0, 524287(15,1)
+ alg 15, 0
#CHECK: algf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x1a]
#CHECK: algf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x1a]
@@ -479,6 +528,19 @@
algr %r15,%r0
algr %r7,%r8
+#CHECK: algsi -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x7e]
+#CHECK: algsi -1, 0 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x7e]
+#CHECK: algsi 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 1, 0 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x7e]
+#CHECK: algsi 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x7e]
+#CHECK: algsi 0, -128 # encoding: [0xeb,0x80,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 0, -1 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 0, 1 # encoding: [0xeb,0x01,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 0, 127 # encoding: [0xeb,0x7f,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 0(%r1), 42 # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x7e]
+#CHECK: algsi 0(%r15), 42 # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x7e]
+#CHECK: algsi 524287(%r1), 42 # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x7e]
+#CHECK: algsi 524287(%r15), 42 # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x7e]
#CHECK: algsi -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x7e]
#CHECK: algsi -1, 0 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x7e]
#CHECK: algsi 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x7e]
@@ -506,6 +568,19 @@
algsi 0(%r15), 42
algsi 524287(%r1), 42
algsi 524287(%r15), 42
+ algsi -524288, 0
+ algsi -1, 0
+ algsi 0, 0
+ algsi 1, 0
+ algsi 524287, 0
+ algsi 0, -128
+ algsi 0, -1
+ algsi 0, 1
+ algsi 0, 127
+ algsi 0(1), 42
+ algsi 0(15), 42
+ algsi 524287(1), 42
+ algsi 524287(15), 42
#CHECK: alr %r0, %r0 # encoding: [0x1e,0x00]
#CHECK: alr %r0, %r15 # encoding: [0x1e,0x0f]
@@ -596,6 +671,20 @@
ap 0(16,%r15), 0(1)
ap 0(1), 0(16,%r1)
ap 0(1), 0(16,%r15)
+ ap 0(1), 0(1)
+ ap 0(1), 0(1,1)
+ ap 0(1), 0(1,15)
+ ap 0(1), 4095(1)
+ ap 0(1), 4095(1,1)
+ ap 0(1), 4095(1,15)
+ ap 0(1,1), 0(1)
+ ap 0(1,15), 0(1)
+ ap 4095(1,1), 0(1)
+ ap 4095(1,15), 0(1)
+ ap 0(16,1), 0(1)
+ ap 0(16,15), 0(1)
+ ap 0(1), 0(16,1)
+ ap 0(1), 0(16,15)
#CHECK: ar %r0, %r0 # encoding: [0x1a,0x00]
#CHECK: ar %r0, %r15 # encoding: [0x1a,0x0f]
diff --git a/llvm/test/MC/SystemZ/regs-good.s b/llvm/test/MC/SystemZ/regs-good.s
index c6157b5e2c85..b4c1edd1b591 100644
--- a/llvm/test/MC/SystemZ/regs-good.s
+++ b/llvm/test/MC/SystemZ/regs-good.s
@@ -152,6 +152,29 @@
lctl %c14,%c15,0
lctl 0,15,0
+#CHECK: st %r0, 0 # encoding: [0x50,0x00,0x00,0x00]
+#CHECK: st %r0, 4095 # encoding: [0x50,0x00,0x0f,0xff]
+#CHECK: st %r0, 0(%r1) # encoding: [0x50,0x00,0x10,0x00]
+#CHECK: st %r0, 0(%r15) # encoding: [0x50,0x00,0xf0,0x00]
+#CHECK: st %r0, 4095(%r1,%r15) # encoding: [0x50,0x01,0xff,0xff]
+#CHECK: st %r0, 4095(%r15,%r1) # encoding: [0x50,0x0f,0x1f,0xff]
+#CHECK: st %r15, 0 # encoding: [0x50,0xf0,0x00,0x00]
+#CHECK: st %r0, 0(%r1) # encoding: [0x50,0x00,0x10,0x00]
+#CHECK: st %r0, 0(%r15) # encoding: [0x50,0x00,0xf0,0x00]
+#CHECK: st %r0, 4095(%r1,%r15) # encoding: [0x50,0x01,0xff,0xff]
+#CHECK: st %r0, 4095(%r15,%r1) # encoding: [0x50,0x0f,0x1f,0xff]
+
+ st %r0, 0
+ st %r0, 4095
+ st %r0, 0(%r1)
+ st %r0, 0(%r15)
+ st %r0, 4095(%r1,%r15)
+ st %r0, 4095(%r15,%r1)
+ st %r15, 0
+ st 0, 0(1)
+ st 0, 0(15)
+ st 0, 4095(1,15)
+ st 0, 4095(15,1)
#CHECK: .cfi_offset %r0, 0
#CHECK: .cfi_offset %r1, 8
diff --git a/llvm/test/MC/SystemZ/tokens.s b/llvm/test/MC/SystemZ/tokens.s
index 177378615ed4..bf8c4e906785 100644
--- a/llvm/test/MC/SystemZ/tokens.s
+++ b/llvm/test/MC/SystemZ/tokens.s
@@ -57,6 +57,14 @@
#CHECK: foo %, 200
#CHECK: error: unknown token in expression
#CHECK: foo {, 200
+#CHECK: error: invalid instruction
+#CHECK: foo 100(15), 300
+#CHECK: error: register expected
+#CHECK: foo 100(15,), 300
+#CHECK: error: invalid instruction
+#CHECK: foo 100(15,%r1), 300
+#CHECK: error: invalid instruction
+#CHECK: foo 100(%v20,10), 300
foo 100, 200
foo 100(, 200
@@ -86,3 +94,7 @@
foo %c, 200
foo %, 200
foo {, 200
+ foo 100(15), 300
+ foo 100(15,), 300
+ foo 100(15,%r1), 300
+ foo 100(%v20,10), 300
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