[PATCH] D82709: [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

In D82709#2137756 <https://reviews.llvm.org/D82709#2137756>, @efriedma wrote:

> > But unfortunately, RA can not sink down the hoisted rematerializable instruction(LIS), so there are still many spills.
>
> "Cannot", as in the target hooks for remat forbid it somehow?  Or are the heuristics somehow favoring spilling over remat?
>
> If we trust the register allocator to remat appropriately, we can just hoist everything without worrying about it.  If we can't trust the register allocator, that means we're assuming the instruction won't be rematerialized, so we shouldn't be checking if it's rematerializable in the first place.


Rereading this, I should probably say a bit more.  I think the patch in https://reviews.llvm.org/D82709#2121904 makes sense in a world where we trust the register allocator.  In a world where we don't trust the register allocator, we should just delete the isTriviallyReMaterializable() check completely.  Either way, we need a consistent model.  The original patch is essentially saying remat only works for instructions that have non-loop-invariant operands, and that doesn't really make sense.

-------

Not really related to the contents of this patch, but some targets, like ARM, use a pseudo-instruction for integer immediates, and expand it after register allocation; this makes remat more effective.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82709/new/

https://reviews.llvm.org/D82709