[llvm] 62ba48b - [PowerPC] Implement Vector Replace Builtins in LLVM

[Lei Huang via llvm-commits]

Author: Biplob Mishra
Date: 2020-07-07T12:22:52-05:00
New Revision: 62ba48b45f6525a3e453b54a6e5562d2f3dc7324

URL: https://github.com/llvm/llvm-project/commit/62ba48b45f6525a3e453b54a6e5562d2f3dc7324
DIFF: https://github.com/llvm/llvm-project/commit/62ba48b45f6525a3e453b54a6e5562d2f3dc7324.diff

LOG: [PowerPC] Implement Vector Replace Builtins in LLVM

Provide the LLVM intrinsics needed to implement vector replace element
builtins in altivec.h which will be added in a subsequent patch.

Differential Revision: https://reviews.llvm.org/D83308

Added: 
    

Modified: 
    llvm/include/llvm/IR/IntrinsicsPowerPC.td
    llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 6aa0c351e95a..12f4a3ce8e28 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -522,6 +522,15 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
               Intrinsic<[llvm_v4i32_ty],
                         [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
                         [IntrNoMem]>;
+  // P10 Vector Insert with immediate.
+  def int_ppc_altivec_vinsw :
+              Intrinsic<[llvm_v4i32_ty],
+                        [llvm_v4i32_ty, llvm_i64_ty, llvm_i32_ty],
+                        [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+  def int_ppc_altivec_vinsd :
+              Intrinsic<[llvm_v2i64_ty],
+                        [llvm_v2i64_ty, llvm_i64_ty, llvm_i32_ty],
+                        [IntrNoMem, ImmArg<ArgIndex<2>>]>;
 }
 
 // Vector average.

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 3ed651abe453..2c21d0a175ad 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -794,8 +794,16 @@ let Predicates = [IsISA3_1] in {
                                       (int_ppc_altivec_vsrdbi v16i8:$VRA,
                                                               v16i8:$VRB, 
                                                               i32:$SH))]>;
-  def VINSW : VXForm_VRT5_UIM5_RB5_ins<207, "vinsw", []>;
-  def VINSD : VXForm_VRT5_UIM5_RB5_ins<463, "vinsd", []>;
+  def VINSW : 
+    VXForm_VRT5_UIM5_RB5_ins<207, "vinsw",
+                             [(set v4i32:$vD,
+                                   (int_ppc_altivec_vinsw v4i32:$vDi, i64:$rB,
+                                                          timm:$UIM))]>;
+  def VINSD :
+    VXForm_VRT5_UIM5_RB5_ins<463, "vinsd",
+                             [(set v2i64:$vD,
+                                   (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB,
+                                                          timm:$UIM))]>;
   def VINSBVLX :
     VXForm_VTB5_RA5_ins<15, "vinsbvlx",
                         [(set v16i8:$vD,

diff  --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
index 577bb212f018..84bf4032aa34 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
@@ -231,3 +231,25 @@ entry:
   ret <4 x i32> %0
 }
 declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>)
+
+define <4 x i32> @testVINSW(<4 x i32> %a, i64 %b) {
+; CHECK-LABEL: testVINSW:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsw v2, r5, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i64 %b, i32 1)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i64, i32 immarg)
+
+define <2 x i64> @testVINSD(<2 x i64> %a, i64 %b) {
+; CHECK-LABEL: testVINSD:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsd v2, r5, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> %a, i64 %b, i32 1)
+  ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64>, i64, i32 immarg)