[PATCH] D82871: [SVE] Custom ISel for fixed length extract/insert_subvector.

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll:25
+; how fixed length operation are lowered to scalable ones, with multiple blocks
+; ensuring insert/extract sequences are not folded away.
+
----------------
paulwalker-arm wrote:
> cameron.mcinally wrote:
> > Nit: could probably mark the loads/stores volatile to avoid the branch.
> I'm not sure how this helps.  The reason for the branch is to force a block boundary to ensure the extract_subvector resulting from lowering the load is not combined with the insert_subvector that's created when lowering the store.
Ok, that makes sense. Let me ask the opposite though -- if the load and store are volatile, will the fixed-width lowering honor the volatile?

```
x = load volatile *p
y = fneg x
x = load volatile *p
store *p, x
```
 
Unlikely a problem considering the loads made it to the backend, but would be good to confirm.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82871/new/

https://reviews.llvm.org/D82871