[PATCH] D60413: [AggressiveInstCombine] SExt -> ZExt when no sign bits is used with multiple uses

[Nikita Popov via Phabricator via llvm-commits]

nikic added inline comments.


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Comment at: llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp:356
+  AssumptionCache AC(F);
+  DemandedBits DB(F, AC, DT);
   for (BasicBlock &BB : F) {
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It's quite likely that this analysis may get invalidated by some of the performed transforms. AssumptionCache should also be made a pass dependency, not constructed inline.

But as mentioned, I would recommend moving this into BDCE instead.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D60413/new/

https://reviews.llvm.org/D60413