[PATCH] D77251: [llvm][CodeGen] Addressing modes for SVE ldN.

Francesco Petrogalli via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 6 19:54:07 PDT 2020


fpetrogalli updated this revision to Diff 275892.
fpetrogalli added a comment.

I have rebased on top of master and added the bfloat test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77251/new/

https://reviews.llvm.org/D77251

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+imm-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+reg-addr-mode.ll

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