[PATCH] D83181: [x86] improve codegen for non-splat bit-masked vector compare and select (PR46531)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:40260
+        TLI.isTypeLegal(VT) && ((Subtarget.hasAVX() && EltBitWidth == 32) ||
+                                (Subtarget.hasAVX2() && EltBitWidth == 64));
+    if (CanShiftBlend &&
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XOP has more vector shifts and vpcmov which should allow 8/16-bit cases as well - I added testing at rGd6c72bdca2f2


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83181/new/

https://reviews.llvm.org/D83181