[llvm] 1c9d681 - [AMDGPU][CODEGEN] Added support of new inline assembler constraints
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 2 07:20:45 PDT 2020
Author: Dmitry Preobrazhensky
Date: 2020-07-02T17:20:15+03:00
New Revision: 1c9d681092d18bac249f01c5d9055dce6898a861
URL: https://github.com/llvm/llvm-project/commit/1c9d681092d18bac249f01c5d9055dce6898a861
DIFF: https://github.com/llvm/llvm-project/commit/1c9d681092d18bac249f01c5d9055dce6898a861.diff
LOG: [AMDGPU][CODEGEN] Added support of new inline assembler constraints
Added support for constraints 'I', 'J', 'B', 'C', 'DA', 'DB'.
See https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints.
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D81651
Added:
Modified:
llvm/docs/LangRef.rst
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.h
llvm/test/CodeGen/AMDGPU/inline-constraints.ll
Removed:
################################################################################
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 0b2a908b9c65..f8eaf881b90a 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -4146,7 +4146,13 @@ AMDGPU:
- ``[0-9]v``: The 32-bit VGPR register, number 0-9.
- ``[0-9]s``: The 32-bit SGPR register, number 0-9.
- ``[0-9]a``: The 32-bit AGPR register, number 0-9.
+- ``I``: An integer inline constant in the range from -16 to 64.
+- ``J``: A 16-bit signed integer constant.
- ``A``: An integer or a floating-point inline constant.
+- ``B``: A 32-bit signed integer constant.
+- ``C``: A 32-bit unsigned integer constant or an integer inline constant in the range from -16 to 64.
+- ``DA``: A 64-bit constant that can be split into two "A" constants.
+- ``DB``: A 64-bit constant that can be split into two "B" constants.
All ARM modes:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index a5a5b7c5f6e1..eef8fe2fc3b7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1365,9 +1365,9 @@ bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
if (AMDGPU::isInlinableIntLiteral(Val)) {
O << Val;
} else if (isUInt<16>(Val)) {
- O << format("0x%" PRIx64, static_cast<uint16_t>(Val));
+ O << format("0x%" PRIx16, static_cast<uint16_t>(Val));
} else if (isUInt<32>(Val)) {
- O << format("0x%" PRIx64, static_cast<uint32_t>(Val));
+ O << format("0x%" PRIx32, static_cast<uint32_t>(Val));
} else {
O << format("0x%" PRIx64, static_cast<uint64_t>(Val));
}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 58de14793cc2..08eda86f1b94 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11163,6 +11163,24 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
}
+static bool isImmConstraint(StringRef Constraint) {
+ if (Constraint.size() == 1) {
+ switch (Constraint[0]) {
+ default: break;
+ case 'I':
+ case 'J':
+ case 'A':
+ case 'B':
+ case 'C':
+ return true;
+ }
+ } else if (Constraint == "DA" ||
+ Constraint == "DB") {
+ return true;
+ }
+ return false;
+}
+
SITargetLowering::ConstraintType
SITargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
@@ -11172,67 +11190,115 @@ SITargetLowering::getConstraintType(StringRef Constraint) const {
case 'v':
case 'a':
return C_RegisterClass;
- case 'A':
- return C_Other;
}
}
+ if (isImmConstraint(Constraint)) {
+ return C_Other;
+ }
return TargetLowering::getConstraintType(Constraint);
}
+static uint64_t clearUnusedBits(uint64_t Val, unsigned Size) {
+ if (!AMDGPU::isInlinableIntLiteral(Val)) {
+ Val = Val & maskTrailingOnes<uint64_t>(Size);
+ }
+ return Val;
+}
+
void SITargetLowering::LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const {
- if (Constraint.length() == 1 && Constraint[0] == 'A') {
- LowerAsmOperandForConstraintA(Op, Ops, DAG);
+ if (isImmConstraint(Constraint)) {
+ uint64_t Val;
+ if (getAsmOperandConstVal(Op, Val) &&
+ checkAsmConstraintVal(Op, Constraint, Val)) {
+ Val = clearUnusedBits(Val, Op.getScalarValueSizeInBits());
+ Ops.push_back(DAG.getTargetConstant(Val, SDLoc(Op), MVT::i64));
+ }
} else {
TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
}
}
-void SITargetLowering::LowerAsmOperandForConstraintA(SDValue Op,
- std::vector<SDValue> &Ops,
- SelectionDAG &DAG) const {
+bool SITargetLowering::getAsmOperandConstVal(SDValue Op, uint64_t &Val) const {
unsigned Size = Op.getScalarValueSizeInBits();
if (Size > 64)
- return;
+ return false;
+
+ if (Size == 16 && !Subtarget->has16BitInsts())
+ return false;
- uint64_t Val;
- bool IsConst = false;
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Val = C->getSExtValue();
- IsConst = true;
- } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op)) {
+ return true;
+ }
+ if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op)) {
Val = C->getValueAPF().bitcastToAPInt().getSExtValue();
- IsConst = true;
- } else if (BuildVectorSDNode *V = dyn_cast<BuildVectorSDNode>(Op)) {
+ return true;
+ }
+ if (BuildVectorSDNode *V = dyn_cast<BuildVectorSDNode>(Op)) {
if (Size != 16 || Op.getNumOperands() != 2)
- return;
+ return false;
if (Op.getOperand(0).isUndef() || Op.getOperand(1).isUndef())
- return;
+ return false;
if (ConstantSDNode *C = V->getConstantSplatNode()) {
Val = C->getSExtValue();
- IsConst = true;
- } else if (ConstantFPSDNode *C = V->getConstantFPSplatNode()) {
+ return true;
+ }
+ if (ConstantFPSDNode *C = V->getConstantFPSplatNode()) {
Val = C->getValueAPF().bitcastToAPInt().getSExtValue();
- IsConst = true;
+ return true;
}
}
- if (IsConst) {
- bool HasInv2Pi = Subtarget->hasInv2PiInlineImm();
- if ((Size == 16 && AMDGPU::isInlinableLiteral16(Val, HasInv2Pi)) ||
- (Size == 32 && AMDGPU::isInlinableLiteral32(Val, HasInv2Pi)) ||
- (Size == 64 && AMDGPU::isInlinableLiteral64(Val, HasInv2Pi))) {
- // Clear unused bits of fp constants
- if (!AMDGPU::isInlinableIntLiteral(Val)) {
- unsigned UnusedBits = 64 - Size;
- Val = (Val << UnusedBits) >> UnusedBits;
- }
- auto Res = DAG.getTargetConstant(Val, SDLoc(Op), MVT::i64);
- Ops.push_back(Res);
+ return false;
+}
+
+bool SITargetLowering::checkAsmConstraintVal(SDValue Op,
+ const std::string &Constraint,
+ uint64_t Val) const {
+ if (Constraint.size() == 1) {
+ switch (Constraint[0]) {
+ case 'I':
+ return AMDGPU::isInlinableIntLiteral(Val);
+ case 'J':
+ return isInt<16>(Val);
+ case 'A':
+ return checkAsmConstraintValA(Op, Val);
+ case 'B':
+ return isInt<32>(Val);
+ case 'C':
+ return isUInt<32>(clearUnusedBits(Val, Op.getScalarValueSizeInBits())) ||
+ AMDGPU::isInlinableIntLiteral(Val);
+ default:
+ break;
+ }
+ } else if (Constraint.size() == 2) {
+ if (Constraint == "DA") {
+ int64_t HiBits = static_cast<int32_t>(Val >> 32);
+ int64_t LoBits = static_cast<int32_t>(Val);
+ return checkAsmConstraintValA(Op, HiBits, 32) &&
+ checkAsmConstraintValA(Op, LoBits, 32);
+ }
+ if (Constraint == "DB") {
+ return true;
}
}
+ llvm_unreachable("Invalid asm constraint");
+}
+
+bool SITargetLowering::checkAsmConstraintValA(SDValue Op,
+ uint64_t Val,
+ unsigned MaxSize) const {
+ unsigned Size = std::min<unsigned>(Op.getScalarValueSizeInBits(), MaxSize);
+ bool HasInv2Pi = Subtarget->hasInv2PiInlineImm();
+ if ((Size == 16 && AMDGPU::isInlinableLiteral16(Val, HasInv2Pi)) ||
+ (Size == 32 && AMDGPU::isInlinableLiteral32(Val, HasInv2Pi)) ||
+ (Size == 64 && AMDGPU::isInlinableLiteral64(Val, HasInv2Pi))) {
+ return true;
+ }
+ return false;
}
// Figure out which registers should be reserved for stack access. Only after
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 7fbd8280efe9..ffe9140d3d07 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -397,9 +397,13 @@ class SITargetLowering final : public AMDGPUTargetLowering {
std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- void LowerAsmOperandForConstraintA(SDValue Op,
- std::vector<SDValue> &Ops,
- SelectionDAG &DAG) const;
+ bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
+ bool checkAsmConstraintVal(SDValue Op,
+ const std::string &Constraint,
+ uint64_t Val) const;
+ bool checkAsmConstraintValA(SDValue Op,
+ uint64_t Val,
+ unsigned MaxSize = 64) const;
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
SDValue V) const;
diff --git a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll
index 63585ebc9553..dc1d44295961 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll
@@ -347,3 +347,971 @@ define i32 @inline_A_constraint_E2() {
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i128 100000000000000000000)
ret i32 %v0
}
+
+;==============================================================================
+; 'I' constraint, 16-bit operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'I'
+; VI-LABEL: {{^}}inline_I_constraint_H0:
+; VI: v_mov_b32 {{v[0-9]+}}, 64
+define i32 @inline_I_constraint_H0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i16 64)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'I'
+; VI-LABEL: {{^}}inline_I_constraint_H1:
+; VI: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_I_constraint_H1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(half bitcast (i16 -16 to half))
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_H6() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(half 1.0)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_H7() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i16 bitcast (half -1.0 to i16))
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_H8() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i16 -17)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_H9() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i16 65)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'I' constraint, 32-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_I_constraint_F0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_I_constraint_F0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i32 -16)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_I_constraint_F1:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_I_constraint_F1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(float bitcast (i32 -1 to float))
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_F8() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(float -4.0)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_F9() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i32 -17)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'I' constraint, 64-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_I_constraint_D0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_I_constraint_D0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i64 -16)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_D8() {
+ %v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,I"(double 0.5)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_D9() {
+ %v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,I"(i64 65)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'I' constraint, v2x16 operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'I'
+; VI-LABEL: {{^}}inline_I_constraint_V0:
+; VI: v_mov_b32 {{v[0-9]+}}, -4
+define i32 @inline_I_constraint_V0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i16> <i16 -4, i16 -4>)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_V1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x half> <half -0.5, half -0.5>)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_V2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i16> <i16 -4, i16 undef>)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_V3() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i16> <i16 1, i16 2>)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_V4() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<4 x i16> <i16 0, i16 0, i16 0, i16 0>)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_V5() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i32> <i32 0, i32 0>)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'I' constraint, type errors
+;==============================================================================
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_E1(i32 %x) {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i32 %x)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'I'
+define i32 @inline_I_constraint_E2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i128 100000000000000000000)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'J' constraint, 16-bit operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'J'
+; VI-LABEL: {{^}}inline_J_constraint_H0:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_J_constraint_H0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i16 65535)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'J'
+; VI-LABEL: {{^}}inline_J_constraint_H1:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_J_constraint_H1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i16 32767)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'J'
+; VI-LABEL: {{^}}inline_J_constraint_H2:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
+define i32 @inline_J_constraint_H2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i16 -32768)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'J'
+; VI-LABEL: {{^}}inline_J_constraint_H3:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x4800
+define i32 @inline_J_constraint_H3() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(half 8.0)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'J'
+; VI-LABEL: {{^}}inline_J_constraint_H4:
+; VI: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_J_constraint_H4() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(half bitcast (i16 -16 to half))
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'J' constraint, 32-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_J_constraint_F0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_J_constraint_F0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 -1)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_J_constraint_F1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_J_constraint_F1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 32767)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_J_constraint_F2:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0xffff8000
+define i32 @inline_J_constraint_F2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 -32768)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'J'
+define i32 @inline_J_constraint_F6() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 32768)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'J'
+define i32 @inline_J_constraint_F7() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 -32769)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'J'
+define i32 @inline_J_constraint_F8() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(float -4.0)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'J' constraint, 64-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_J_constraint_D0:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_J_constraint_D0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i64 32767)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_J_constraint_D1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0xffffffffffff8000
+define i32 @inline_J_constraint_D1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i64 -32768)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'J'
+define i32 @inline_J_constraint_D8() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i64 32768)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'J'
+define i32 @inline_J_constraint_D9() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i64 -32769)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'J' constraint, v2x16 operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'J'
+; VI-LABEL: {{^}}inline_J_constraint_V0:
+; VI: v_mov_b32 {{v[0-9]+}}, -4
+define i32 @inline_J_constraint_V0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(<2 x i16> <i16 -4, i16 -4>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'J'
+; VI-LABEL: {{^}}inline_J_constraint_V1:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_J_constraint_V1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(<2 x i16> <i16 32767, i16 32767>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'J'
+; VI-LABEL: {{^}}inline_J_constraint_V2:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
+define i32 @inline_J_constraint_V2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(<2 x i16> <i16 -32768, i16 -32768>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'J'
+; VI-LABEL: {{^}}inline_J_constraint_V3:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x4c00
+define i32 @inline_J_constraint_V3() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(<2 x half> <half 16.0, half 16.0>)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'J' constraint, type errors
+;==============================================================================
+
+; NOGCN: error: invalid operand for inline asm constraint 'J'
+define i32 @inline_J_constraint_E1(i32 %x) {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 %x)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'J'
+define i32 @inline_J_constraint_E2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i128 100000000000000000000)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'B' constraint, 16-bit operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'B'
+; VI-LABEL: {{^}}inline_B_constraint_H0:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_B_constraint_H0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i16 32767)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'B'
+; VI-LABEL: {{^}}inline_B_constraint_H1:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_B_constraint_H1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i16 65535)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'B'
+; VI-LABEL: {{^}}inline_B_constraint_H3:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
+define i32 @inline_B_constraint_H3() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i16 -32768)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'B'
+; VI-LABEL: {{^}}inline_B_constraint_H4:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x4a80
+define i32 @inline_B_constraint_H4() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(half 13.0)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'B' constraint, 32-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_B_constraint_F0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_B_constraint_F0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i32 4294967295)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_B_constraint_F1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x80000000
+define i32 @inline_B_constraint_F1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i32 2147483648)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_B_constraint_F2:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x42000000
+define i32 @inline_B_constraint_F2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(float 32.0)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'B' constraint, 64-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_B_constraint_D0:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fffffff
+define i32 @inline_B_constraint_D0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 2147483647)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_B_constraint_D1:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_B_constraint_D1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 -1)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_B_constraint_D2:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0xffffffff80000000
+define i32 @inline_B_constraint_D2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 -2147483648)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'B'
+define i32 @inline_B_constraint_D7() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 -2147483649)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'B'
+define i32 @inline_B_constraint_D8() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 4294967295)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'B'
+define i32 @inline_B_constraint_D9() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 2147483648)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'B' constraint, v2x16 operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'B'
+; VI-LABEL: {{^}}inline_B_constraint_V0:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_B_constraint_V0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(<2 x i16> <i16 32767, i16 32767>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'B'
+; VI-LABEL: {{^}}inline_B_constraint_V1:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_B_constraint_V1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(<2 x i16> <i16 -1, i16 -1>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'B'
+; VI-LABEL: {{^}}inline_B_constraint_V2:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
+define i32 @inline_B_constraint_V2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(<2 x i16> <i16 -32768, i16 -32768>)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'C' constraint, 16-bit operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'C'
+; VI-LABEL: {{^}}inline_C_constraint_H0:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_C_constraint_H0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i16 32767)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'C'
+; VI-LABEL: {{^}}inline_C_constraint_H1:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_C_constraint_H1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i16 65535)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'C'
+; VI-LABEL: {{^}}inline_C_constraint_H3:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
+define i32 @inline_C_constraint_H3() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i16 -32768)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'C'
+; VI-LABEL: {{^}}inline_C_constraint_H4:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x4a80
+define i32 @inline_C_constraint_H4() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(half 13.0)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'C' constraint, 32-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_C_constraint_F0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_C_constraint_F0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 4294967295)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_C_constraint_F1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x80000000
+define i32 @inline_C_constraint_F1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 2147483648)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_C_constraint_F2:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fffffff
+define i32 @inline_C_constraint_F2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 2147483647)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_C_constraint_F3:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x42000000
+define i32 @inline_C_constraint_F3() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(float 32.0)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_C_constraint_F4:
+; GCN: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_C_constraint_F4() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 -16)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_C_constraint_F5:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0xffffffef
+define i32 @inline_C_constraint_F5() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 -17)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'C' constraint, 64-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_C_constraint_D0:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0xffffffff
+define i32 @inline_C_constraint_D0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 4294967295)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_C_constraint_D1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x80000000
+define i32 @inline_C_constraint_D1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 2147483648)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_C_constraint_D2:
+; GCN: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_C_constraint_D2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 -16)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'C'
+define i32 @inline_C_constraint_D8() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 -17)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'C'
+define i32 @inline_C_constraint_D9() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 4294967296)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'C' constraint, v2x16 operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'C'
+; VI-LABEL: {{^}}inline_C_constraint_V0:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_C_constraint_V0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(<2 x i16> <i16 32767, i16 32767>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'C'
+; VI-LABEL: {{^}}inline_C_constraint_V1:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_C_constraint_V1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(<2 x i16> <i16 -1, i16 -1>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'C'
+; VI-LABEL: {{^}}inline_C_constraint_V2:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
+define i32 @inline_C_constraint_V2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(<2 x i16> <i16 -32768, i16 -32768>)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DA' constraint, 16-bit operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_H0:
+; VI: v_mov_b32 {{v[0-9]+}}, 64
+define i32 @inline_DA_constraint_H0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 64)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_H1:
+; VI: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_DA_constraint_H1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 -16)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_H2:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x3c00
+define i32 @inline_DA_constraint_H2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 bitcast (half 1.0 to i16))
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_H3:
+; VI: v_mov_b32 {{v[0-9]+}}, 0xbc00
+define i32 @inline_DA_constraint_H3() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 bitcast (half -1.0 to i16))
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_H4:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x3118
+define i32 @inline_DA_constraint_H4() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(half 0xH3118)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_H5:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x3118
+define i32 @inline_DA_constraint_H5() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 bitcast (half 0xH3118 to i16))
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_H6:
+; VI: v_mov_b32 {{v[0-9]+}}, 0xb800
+define i32 @inline_DA_constraint_H6() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(half -0.5)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_H7() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 bitcast (half 0xH3119 to i16))
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_H8() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 -17)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_H9() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 65)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DA' constraint, 32-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_DA_constraint_F0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_DA_constraint_F0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 -16)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DA_constraint_F1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 1
+define i32 @inline_DA_constraint_F1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 1)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DA_constraint_F2:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0xbf000000
+define i32 @inline_DA_constraint_F2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 bitcast (float -0.5 to i32))
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DA_constraint_F3:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x40000000
+define i32 @inline_DA_constraint_F3() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 bitcast (float 2.0 to i32))
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DA_constraint_F4:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0xc0800000
+define i32 @inline_DA_constraint_F4() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(float -4.0)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_F5:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x3e22f983
+define i32 @inline_DA_constraint_F5() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 1042479491)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DA_constraint_F6:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x3f000000
+define i32 @inline_DA_constraint_F6() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(float 0.5)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_F7() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 65)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_F8() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 -17)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DA' constraint, 64-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_DA_constraint_D0:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x40fffffff0
+define i32 @inline_DA_constraint_D0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0x40fffffff0 to i64))
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DA_constraint_D1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0xfffffff000000040
+define i32 @inline_DA_constraint_D1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0xfffffff000000040 to i64))
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DA_constraint_D2:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_DA_constraint_D2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 -1)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DA_constraint_D3:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0xbf000000c0800000
+define i32 @inline_DA_constraint_D3() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0xbf000000c0800000 to i64))
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_D4:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x3e22f9833e22f983
+define i32 @inline_DA_constraint_D4() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0x3e22f9833e22f983 to i64))
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_D5() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0x0000004000000041 to i64))
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_D8() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0x0000004100000040 to i64))
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_D9() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(double 100.0)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DA' constraint, v2x16 operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_V0:
+; VI: v_mov_b32 {{v[0-9]+}}, -4
+define i32 @inline_DA_constraint_V0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x i16> <i16 -4, i16 -4>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DA'
+; VI-LABEL: {{^}}inline_DA_constraint_V1:
+; VI: v_mov_b32 {{v[0-9]+}}, 0xb800
+define i32 @inline_DA_constraint_V1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x half> <half -0.5, half -0.5>)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_V2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x i16> <i16 -4, i16 undef>)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_V6() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x i32> <i32 0, i32 0>)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DA' constraint, type errors
+;==============================================================================
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_E1(i32 %x) {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 %x)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DA'
+define i32 @inline_DA_constraint_E2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i128 100000000000000000000)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DB' constraint, 16-bit operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'DB'
+; VI-LABEL: {{^}}inline_DB_constraint_H0:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_DB_constraint_H0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i16 32767)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DB'
+; VI-LABEL: {{^}}inline_DB_constraint_H1:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_DB_constraint_H1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i16 65535)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DB'
+; VI-LABEL: {{^}}inline_DB_constraint_H2:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x4a80
+define i32 @inline_DB_constraint_H2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(half 13.0)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DB' constraint, 32-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_DB_constraint_F0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_DB_constraint_F0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i32 4294967295)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DB_constraint_F1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x80000000
+define i32 @inline_DB_constraint_F1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i32 2147483648)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DB_constraint_F2:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x42000000
+define i32 @inline_DB_constraint_F2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(float 32.0)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DB' constraint, 64-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_DB_constraint_D0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_DB_constraint_D0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DB"(i64 -1)
+ ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_DB_constraint_D1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x1234567890abcdef
+define i32 @inline_DB_constraint_D1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DB"(i64 bitcast (double 0x1234567890abcdef to i64))
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DB' constraint, v2x16 operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'DB'
+; VI-LABEL: {{^}}inline_DB_constraint_V0:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_DB_constraint_V0() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(<2 x i16> <i16 32767, i16 32767>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DB'
+; VI-LABEL: {{^}}inline_DB_constraint_V1:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_DB_constraint_V1() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(<2 x i16> <i16 65535, i16 65535>)
+ ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'DB'
+; VI-LABEL: {{^}}inline_DB_constraint_V2:
+; VI: v_mov_b32 {{v[0-9]+}}, 0xd640
+define i32 @inline_DB_constraint_V2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(<2 x half> <half -100.0, half -100.0>)
+ ret i32 %v0
+}
+
+;==============================================================================
+; 'DB' constraint, type errors
+;==============================================================================
+
+; NOGCN: error: invalid operand for inline asm constraint 'DB'
+define i32 @inline_DB_constraint_E1(i32 %x) {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i32 %x)
+ ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'DB'
+define i32 @inline_DB_constraint_E2() {
+ %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i128 100000000000000000000)
+ ret i32 %v0
+}
More information about the llvm-commits
mailing list