[llvm] 23eeae5 - Regenerate sext/trunc tests and replace %tmp variable names to silence update_test_checks warnings
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 2 06:37:42 PDT 2020
Author: Simon Pilgrim
Date: 2020-07-02T14:37:21+01:00
New Revision: 23eeae552689ecf47dbb5c5dcc551a074c4e0110
URL: https://github.com/llvm/llvm-project/commit/23eeae552689ecf47dbb5c5dcc551a074c4e0110
DIFF: https://github.com/llvm/llvm-project/commit/23eeae552689ecf47dbb5c5dcc551a074c4e0110.diff
LOG: Regenerate sext/trunc tests and replace %tmp variable names to silence update_test_checks warnings
Added:
Modified:
llvm/test/Transforms/InstCombine/sext.ll
llvm/test/Transforms/InstCombine/trunc.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/sext.ll b/llvm/test/Transforms/InstCombine/sext.ll
index faf33719927d..30b8b670491a 100644
--- a/llvm/test/Transforms/InstCombine/sext.ll
+++ b/llvm/test/Transforms/InstCombine/sext.ll
@@ -9,9 +9,9 @@ declare i32 @llvm.cttz.i32(i32, i1)
define i64 @test1(i32 %x) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 %x)
-; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
-; CHECK-NEXT: ret i64 [[S1]]
+; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range !0
+; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S]]
;
%t = call i32 @llvm.ctpop.i32(i32 %x)
%s = sext i32 %t to i64
@@ -20,9 +20,9 @@ define i64 @test1(i32 %x) {
define i64 @test2(i32 %x) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
-; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
-; CHECK-NEXT: ret i64 [[S1]]
+; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range !0
+; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S]]
;
%t = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
%s = sext i32 %t to i64
@@ -31,9 +31,9 @@ define i64 @test2(i32 %x) {
define i64 @test3(i32 %x) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
-; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
-; CHECK-NEXT: ret i64 [[S1]]
+; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range !0
+; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S]]
;
%t = call i32 @llvm.cttz.i32(i32 %x, i1 true)
%s = sext i32 %t to i64
@@ -42,9 +42,9 @@ define i64 @test3(i32 %x) {
define i64 @test4(i32 %x) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[T:%.*]] = udiv i32 %x, 3
-; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
-; CHECK-NEXT: ret i64 [[S1]]
+; CHECK-NEXT: [[T:%.*]] = udiv i32 [[X:%.*]], 3
+; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S]]
;
%t = udiv i32 %x, 3
%s = sext i32 %t to i64
@@ -53,9 +53,9 @@ define i64 @test4(i32 %x) {
define i64 @test5(i32 %x) {
; CHECK-LABEL: @test5(
-; CHECK-NEXT: [[T:%.*]] = urem i32 %x, 30000
-; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
-; CHECK-NEXT: ret i64 [[S1]]
+; CHECK-NEXT: [[T:%.*]] = urem i32 [[X:%.*]], 30000
+; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S]]
;
%t = urem i32 %x, 30000
%s = sext i32 %t to i64
@@ -64,10 +64,10 @@ define i64 @test5(i32 %x) {
define i64 @test6(i32 %x) {
; CHECK-LABEL: @test6(
-; CHECK-NEXT: [[U:%.*]] = lshr i32 %x, 3
+; CHECK-NEXT: [[U:%.*]] = lshr i32 [[X:%.*]], 3
; CHECK-NEXT: [[T:%.*]] = mul nuw nsw i32 [[U]], 3
-; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
-; CHECK-NEXT: ret i64 [[S1]]
+; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S]]
;
%u = lshr i32 %x, 3
%t = mul i32 %u, 3
@@ -77,10 +77,10 @@ define i64 @test6(i32 %x) {
define i64 @test7(i32 %x) {
; CHECK-LABEL: @test7(
-; CHECK-NEXT: [[T:%.*]] = and i32 %x, 511
+; CHECK-NEXT: [[T:%.*]] = and i32 [[X:%.*]], 511
; CHECK-NEXT: [[U:%.*]] = sub nuw nsw i32 20000, [[T]]
-; CHECK-NEXT: [[S1:%.*]] = zext i32 [[U]] to i64
-; CHECK-NEXT: ret i64 [[S1]]
+; CHECK-NEXT: [[S:%.*]] = zext i32 [[U]] to i64
+; CHECK-NEXT: ret i64 [[S]]
;
%t = and i32 %x, 511
%u = sub i32 20000, %t
@@ -90,8 +90,8 @@ define i64 @test7(i32 %x) {
define i32 @test8(i8 %a, i32 %f, i1 %p, i32* %z) {
; CHECK-LABEL: @test8(
-; CHECK-NEXT: [[D:%.*]] = lshr i32 %f, 24
-; CHECK-NEXT: [[N:%.*]] = select i1 %p, i32 [[D]], i32 0
+; CHECK-NEXT: [[D:%.*]] = lshr i32 [[F:%.*]], 24
+; CHECK-NEXT: [[N:%.*]] = select i1 [[P:%.*]], i32 [[D]], i32 0
; CHECK-NEXT: ret i32 [[N]]
;
%d = lshr i32 %f, 24
@@ -127,22 +127,22 @@ F:
; PR2638
define i32 @test10(i32 %i) {
; CHECK-LABEL: @test10(
-; CHECK-NEXT: [[B1:%.*]] = shl i32 %i, 30
-; CHECK-NEXT: [[B:%.*]] = ashr exact i32 [[B1]], 30
-; CHECK-NEXT: ret i32 [[B]]
+; CHECK-NEXT: [[D1:%.*]] = shl i32 [[I:%.*]], 30
+; CHECK-NEXT: [[D:%.*]] = ashr exact i32 [[D1]], 30
+; CHECK-NEXT: ret i32 [[D]]
;
- %tmp12 = trunc i32 %i to i8
- %tmp16 = shl i8 %tmp12, 6
- %a = ashr i8 %tmp16, 6
- %b = sext i8 %a to i32
- ret i32 %b
+ %A = trunc i32 %i to i8
+ %B = shl i8 %A, 6
+ %C = ashr i8 %B, 6
+ %D = sext i8 %C to i32
+ ret i32 %D
}
define void @test11(<2 x i16> %srcA, <2 x i16> %srcB, <2 x i16>* %dst) {
; CHECK-LABEL: @test11(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i16> %srcB, %srcA
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i16> [[SRCB:%.*]], [[SRCA:%.*]]
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i16>
-; CHECK-NEXT: store <2 x i16> [[SEXT]], <2 x i16>* %dst, align 4
+; CHECK-NEXT: store <2 x i16> [[SEXT]], <2 x i16>* [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
%cmp = icmp eq <2 x i16> %srcB, %srcA
@@ -154,7 +154,7 @@ define void @test11(<2 x i16> %srcA, <2 x i16> %srcB, <2 x i16>* %dst) {
define i64 @test12(i32 %x) {
; CHECK-LABEL: @test12(
-; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %x, 1
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 1
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[SHR]]
; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[SUB]] to i64
; CHECK-NEXT: ret i64 [[CONV]]
@@ -167,7 +167,7 @@ define i64 @test12(i32 %x) {
define i32 @test13(i32 %x) {
; CHECK-LABEL: @test13(
-; CHECK-NEXT: [[AND:%.*]] = lshr i32 %x, 3
+; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 3
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 1
; CHECK-NEXT: [[SEXT:%.*]] = add nsw i32 [[TMP1]], -1
; CHECK-NEXT: ret i32 [[SEXT]]
@@ -180,7 +180,7 @@ define i32 @test13(i32 %x) {
define i32 @test14(i16 %x) {
; CHECK-LABEL: @test14(
-; CHECK-NEXT: [[AND:%.*]] = lshr i16 %x, 4
+; CHECK-NEXT: [[AND:%.*]] = lshr i16 [[X:%.*]], 4
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[AND]], 1
; CHECK-NEXT: [[SEXT:%.*]] = add nsw i16 [[TMP1]], -1
; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
@@ -194,8 +194,8 @@ define i32 @test14(i16 %x) {
define i32 @test15(i32 %x) {
; CHECK-LABEL: @test15(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 27
-; CHECK-NEXT: [[SEXT:%.*]] = ashr i32 [[TMP1]], 31
+; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 27
+; CHECK-NEXT: [[SEXT:%.*]] = ashr i32 [[AND]], 31
; CHECK-NEXT: ret i32 [[SEXT]]
;
%and = and i32 %x, 16
@@ -206,8 +206,8 @@ define i32 @test15(i32 %x) {
define i32 @test16(i16 %x) {
; CHECK-LABEL: @test16(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i16 %x, 12
-; CHECK-NEXT: [[SEXT:%.*]] = ashr i16 [[TMP1]], 15
+; CHECK-NEXT: [[AND:%.*]] = shl i16 [[X:%.*]], 12
+; CHECK-NEXT: [[SEXT:%.*]] = ashr i16 [[AND]], 15
; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
; CHECK-NEXT: ret i32 [[EXT]]
;
@@ -219,8 +219,8 @@ define i32 @test16(i16 %x) {
define i32 @test17(i1 %x) {
; CHECK-LABEL: @test17(
-; CHECK-NEXT: [[C2:%.*]] = zext i1 %x to i32
-; CHECK-NEXT: ret i32 [[C2]]
+; CHECK-NEXT: [[C1_NEG:%.*]] = zext i1 [[X:%.*]] to i32
+; CHECK-NEXT: ret i32 [[C1_NEG]]
;
%c1 = sext i1 %x to i32
%c2 = sub i32 0, %c1
@@ -229,10 +229,10 @@ define i32 @test17(i1 %x) {
define i32 @test18(i16 %x) {
; CHECK-LABEL: @test18(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 %x, 0
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[TMP1]], i16 %x, i16 0
-; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[SEL]] to i32
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 [[X:%.*]], 0
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[TMP1]], i16 [[X]], i16 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[SEL]] to i32
+; CHECK-NEXT: ret i32 [[EXT]]
;
%cmp = icmp slt i16 %x, 0
%sel = select i1 %cmp, i16 0, i16 %x
diff --git a/llvm/test/Transforms/InstCombine/trunc.ll b/llvm/test/Transforms/InstCombine/trunc.ll
index d9ad3753e91a..5f62886fb91e 100644
--- a/llvm/test/Transforms/InstCombine/trunc.ll
+++ b/llvm/test/Transforms/InstCombine/trunc.ll
@@ -163,18 +163,18 @@ define i92 @test7(i64 %A) {
define i64 @test8(i32 %A, i32 %B) {
; CHECK-LABEL: @test8(
-; CHECK-NEXT: [[TMP38:%.*]] = zext i32 [[A:%.*]] to i64
-; CHECK-NEXT: [[TMP32:%.*]] = zext i32 [[B:%.*]] to i64
-; CHECK-NEXT: [[TMP33:%.*]] = shl nuw i64 [[TMP32]], 32
-; CHECK-NEXT: [[INS35:%.*]] = or i64 [[TMP33]], [[TMP38]]
-; CHECK-NEXT: ret i64 [[INS35]]
+; CHECK-NEXT: [[C:%.*]] = zext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[D:%.*]] = zext i32 [[B:%.*]] to i64
+; CHECK-NEXT: [[E:%.*]] = shl nuw i64 [[D]], 32
+; CHECK-NEXT: [[F:%.*]] = or i64 [[E]], [[C]]
+; CHECK-NEXT: ret i64 [[F]]
;
- %tmp38 = zext i32 %A to i128
- %tmp32 = zext i32 %B to i128
- %tmp33 = shl i128 %tmp32, 32
- %ins35 = or i128 %tmp33, %tmp38
- %tmp42 = trunc i128 %ins35 to i64
- ret i64 %tmp42
+ %C = zext i32 %A to i128
+ %D = zext i32 %B to i128
+ %E = shl i128 %D, 32
+ %F = or i128 %E, %C
+ %G = trunc i128 %F to i64
+ ret i64 %G
}
define i8 @test9(i32 %X) {
@@ -409,79 +409,79 @@ define void @trunc_shl_31_i32_i64_multi_use(i64 %val, i32 addrspace(1)* %ptr0, i
define i32 @trunc_shl_lshr_infloop(i64 %arg) {
; CHECK-LABEL: @trunc_shl_lshr_infloop(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[ARG:%.*]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[TMP0]], 2
-; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[A:%.*]] = lshr i64 [[ARG:%.*]], 1
+; CHECK-NEXT: [[B:%.*]] = shl i64 [[A]], 2
+; CHECK-NEXT: [[C:%.*]] = trunc i64 [[B]] to i32
+; CHECK-NEXT: ret i32 [[C]]
;
- %tmp0 = lshr i64 %arg, 1
- %tmp1 = shl i64 %tmp0, 2
- %tmp2 = trunc i64 %tmp1 to i32
- ret i32 %tmp2
+ %A = lshr i64 %arg, 1
+ %B = shl i64 %A, 2
+ %C = trunc i64 %B to i32
+ ret i32 %C
}
define i32 @trunc_shl_ashr_infloop(i64 %arg) {
; CHECK-LABEL: @trunc_shl_ashr_infloop(
-; CHECK-NEXT: [[TMP0:%.*]] = ashr i64 [[ARG:%.*]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2
-; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[A:%.*]] = ashr i64 [[ARG:%.*]], 3
+; CHECK-NEXT: [[B:%.*]] = shl nsw i64 [[A]], 2
+; CHECK-NEXT: [[C:%.*]] = trunc i64 [[B]] to i32
+; CHECK-NEXT: ret i32 [[C]]
;
- %tmp0 = ashr i64 %arg, 3
- %tmp1 = shl i64 %tmp0, 2
- %tmp2 = trunc i64 %tmp1 to i32
- ret i32 %tmp2
+ %A = ashr i64 %arg, 3
+ %B = shl i64 %A, 2
+ %C = trunc i64 %B to i32
+ ret i32 %C
}
define i32 @trunc_shl_shl_infloop(i64 %arg) {
; CHECK-LABEL: @trunc_shl_shl_infloop(
; CHECK-NEXT: [[ARG_TR:%.*]] = trunc i64 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[ARG_TR]], 3
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = shl i32 [[ARG_TR]], 3
+; CHECK-NEXT: ret i32 [[C]]
;
- %tmp0 = shl i64 %arg, 1
- %tmp1 = shl i64 %tmp0, 2
- %tmp2 = trunc i64 %tmp1 to i32
- ret i32 %tmp2
+ %A = shl i64 %arg, 1
+ %B = shl i64 %A, 2
+ %C = trunc i64 %B to i32
+ ret i32 %C
}
define i32 @trunc_shl_lshr_var(i64 %arg, i64 %val) {
; CHECK-LABEL: @trunc_shl_lshr_var(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[ARG:%.*]], [[VAL:%.*]]
-; CHECK-NEXT: [[TMP0_TR:%.*]] = trunc i64 [[TMP0]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0_TR]], 2
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[A:%.*]] = lshr i64 [[ARG:%.*]], [[VAL:%.*]]
+; CHECK-NEXT: [[A_TR:%.*]] = trunc i64 [[A]] to i32
+; CHECK-NEXT: [[C:%.*]] = shl i32 [[A_TR]], 2
+; CHECK-NEXT: ret i32 [[C]]
;
- %tmp0 = lshr i64 %arg, %val
- %tmp1 = shl i64 %tmp0, 2
- %tmp2 = trunc i64 %tmp1 to i32
- ret i32 %tmp2
+ %A = lshr i64 %arg, %val
+ %B = shl i64 %A, 2
+ %C = trunc i64 %B to i32
+ ret i32 %C
}
define i32 @trunc_shl_ashr_var(i64 %arg, i64 %val) {
; CHECK-LABEL: @trunc_shl_ashr_var(
-; CHECK-NEXT: [[TMP0:%.*]] = ashr i64 [[ARG:%.*]], [[VAL:%.*]]
-; CHECK-NEXT: [[TMP0_TR:%.*]] = trunc i64 [[TMP0]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0_TR]], 2
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[A:%.*]] = ashr i64 [[ARG:%.*]], [[VAL:%.*]]
+; CHECK-NEXT: [[A_TR:%.*]] = trunc i64 [[A]] to i32
+; CHECK-NEXT: [[C:%.*]] = shl i32 [[A_TR]], 2
+; CHECK-NEXT: ret i32 [[C]]
;
- %tmp0 = ashr i64 %arg, %val
- %tmp1 = shl i64 %tmp0, 2
- %tmp2 = trunc i64 %tmp1 to i32
- ret i32 %tmp2
+ %A = ashr i64 %arg, %val
+ %B = shl i64 %A, 2
+ %C = trunc i64 %B to i32
+ ret i32 %C
}
define i32 @trunc_shl_shl_var(i64 %arg, i64 %val) {
; CHECK-LABEL: @trunc_shl_shl_var(
-; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[ARG:%.*]], [[VAL:%.*]]
-; CHECK-NEXT: [[TMP0_TR:%.*]] = trunc i64 [[TMP0]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0_TR]], 2
-; CHECK-NEXT: ret i32 [[TMP2]]
-;
- %tmp0 = shl i64 %arg, %val
- %tmp1 = shl i64 %tmp0, 2
- %tmp2 = trunc i64 %tmp1 to i32
- ret i32 %tmp2
+; CHECK-NEXT: [[A:%.*]] = shl i64 [[ARG:%.*]], [[VAL:%.*]]
+; CHECK-NEXT: [[A_TR:%.*]] = trunc i64 [[A]] to i32
+; CHECK-NEXT: [[C:%.*]] = shl i32 [[A_TR]], 2
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = shl i64 %arg, %val
+ %B = shl i64 %A, 2
+ %C = trunc i64 %B to i32
+ ret i32 %C
}
define <8 x i16> @trunc_shl_v8i15_v8i32_15(<8 x i32> %a) {
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