[PATCH] D83029: [SVE] Fix invalid assert in expand_DestructiveOp.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.
paulwalker-arm added reviewers: david-arm, sdesmalen.

AArch64ExpandPseudo::expand_DestructiveOp contains an assert to
ensure the destructive operand's register is unique.  However,
this is only required when psuedo expansion emits a movprfx.

A simple example when a movprfx is not required is

  Z0 = FADD_ZPZZ_UNDEF_S P0, Z0, Z0

which expands to an unprefixed FADD_ZPmZ_S instruction.

This patch moves the assert to the places where a movprfx is emitted.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83029

Files:
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir


Index: llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
@@ -0,0 +1,22 @@
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=aarch64-expand-pseudo -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+---
+name:            add_x
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$p0' }
+  - { reg: '$z0' }
+frameInfo:
+  maxCallFrameSize: 0
+body:             |
+  bb.0:
+    liveins: $p0, $z0
+
+    ; CHECK: add_x
+    ; CHECK-NOT: MOVPRFX
+    ; CHECK: $z0 = FADD_ZPmZ_S renamable $p0, killed $z0, renamable $z0
+    ; CHECK-NEXT: RET
+    renamable $z0 = FADD_ZPZZ_UNDEF_S renamable $p0, renamable $z0, killed renamable $z0
+    RET_ReallyLR
+
+...
Index: llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -438,8 +438,6 @@
     DOPRegIsUnique = true;
     break;
   }
-
-  assert (DOPRegIsUnique && "The destructive operand should be unique");
 #endif
 
   // Resolve the reverse opcode
@@ -480,6 +478,9 @@
   //
   MachineInstrBuilder PRFX, DOP;
   if (FalseZero) {
+#ifndef NDEBUG
+    assert(DOPRegIsUnique && "The destructive operand should be unique");
+#endif
     assert(ElementSize != AArch64::ElementSizeNone &&
            "This instruction is unpredicated");
 
@@ -492,6 +493,9 @@
     // After the movprfx, the destructive operand is same as Dst
     DOPIdx = 0;
   } else if (DstReg != MI.getOperand(DOPIdx).getReg()) {
+#ifndef NDEBUG
+    assert(DOPRegIsUnique && "The destructive operand should be unique");
+#endif
     PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfx))
                .addReg(DstReg, RegState::Define)
                .addReg(MI.getOperand(DOPIdx).getReg());


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