[llvm] 07bda98 - [AArch64][SVE] Add unpred load/store patterns for bf16 types
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 2 02:05:51 PDT 2020
Author: Sander de Smalen
Date: 2020-07-02T10:01:24+01:00
New Revision: 07bda98b6afdef7bed0bf7d47f5a8f6cfc64d973
URL: https://github.com/llvm/llvm-project/commit/07bda98b6afdef7bed0bf7d47f5a8f6cfc64d973
DIFF: https://github.com/llvm/llvm-project/commit/07bda98b6afdef7bed0bf7d47f5a8f6cfc64d973.diff
LOG: [AArch64][SVE] Add unpred load/store patterns for bf16 types
Reviewers: kmclaughlin, c-rhodes, efriedma
Reviewed By: efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82909
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/spillfill-sve.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 537e54f3a8d8..dc718b34d01d 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1711,6 +1711,7 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
defm : unpred_store<truncstorevi32, nxv2i64, ST1W_D_IMM, PTRUE_D>;
defm : unpred_store< store, nxv2i64, ST1D_IMM, PTRUE_D>;
defm : unpred_store< store, nxv8f16, ST1H_IMM, PTRUE_H>;
+ defm : unpred_store< store, nxv8bf16, ST1H_IMM, PTRUE_H>;
defm : unpred_store< store, nxv4f16, ST1H_S_IMM, PTRUE_S>;
defm : unpred_store< store, nxv2f16, ST1H_D_IMM, PTRUE_D>;
defm : unpred_store< store, nxv4f32, ST1W_IMM, PTRUE_S>;
@@ -1756,6 +1757,7 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
defm : unpred_load<sextloadvi32, nxv2i64, LD1SW_D_IMM, PTRUE_D>;
defm : unpred_load< load, nxv2i64, LD1D_IMM, PTRUE_D>;
defm : unpred_load< load, nxv8f16, LD1H_IMM, PTRUE_H>;
+ defm : unpred_load< load, nxv8bf16, LD1H_IMM, PTRUE_H>;
defm : unpred_load< load, nxv4f16, LD1H_S_IMM, PTRUE_S>;
defm : unpred_load< load, nxv2f16, LD1H_D_IMM, PTRUE_D>;
defm : unpred_load< load, nxv4f32, LD1W_IMM, PTRUE_S>;
diff --git a/llvm/test/CodeGen/AArch64/spillfill-sve.ll b/llvm/test/CodeGen/AArch64/spillfill-sve.ll
index 92c827b41c3a..a703c510952f 100644
--- a/llvm/test/CodeGen/AArch64/spillfill-sve.ll
+++ b/llvm/test/CodeGen/AArch64/spillfill-sve.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -mattr=+bf16 < %s | FileCheck %s
; This file checks that unpredicated load/store instructions to locals
; use the right instructions and offsets.
@@ -199,6 +199,50 @@ define void @fill_nxv2i64() {
ret void
}
+define void @fill_nxv8bf16() {
+; CHECK-LABEL: fill_nxv8bf16
+; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp]
+; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp, #1, mul vl]
+ %local0 = alloca <vscale x 8 x bfloat>
+ %local1 = alloca <vscale x 8 x bfloat>
+ load volatile <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %local0
+ load volatile <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %local1
+ ret void
+}
+
+define void @fill_nxv8f16() {
+; CHECK-LABEL: fill_nxv8f16
+; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp]
+; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp, #1, mul vl]
+ %local0 = alloca <vscale x 8 x half>
+ %local1 = alloca <vscale x 8 x half>
+ load volatile <vscale x 8 x half>, <vscale x 8 x half>* %local0
+ load volatile <vscale x 8 x half>, <vscale x 8 x half>* %local1
+ ret void
+}
+
+define void @fill_nxv4f32() {
+; CHECK-LABEL: fill_nxv4f32
+; CHECK-DAG: ld1w { z{{[01]}}.s }, p0/z, [sp]
+; CHECK-DAG: ld1w { z{{[01]}}.s }, p0/z, [sp, #1, mul vl]
+ %local0 = alloca <vscale x 4 x float>
+ %local1 = alloca <vscale x 4 x float>
+ load volatile <vscale x 4 x float>, <vscale x 4 x float>* %local0
+ load volatile <vscale x 4 x float>, <vscale x 4 x float>* %local1
+ ret void
+}
+
+define void @fill_nxv2f64() {
+; CHECK-LABEL: fill_nxv2f64
+; CHECK-DAG: ld1d { z{{[01]}}.d }, p0/z, [sp]
+; CHECK-DAG: ld1d { z{{[01]}}.d }, p0/z, [sp, #1, mul vl]
+ %local0 = alloca <vscale x 2 x double>
+ %local1 = alloca <vscale x 2 x double>
+ load volatile <vscale x 2 x double>, <vscale x 2 x double>* %local0
+ load volatile <vscale x 2 x double>, <vscale x 2 x double>* %local1
+ ret void
+}
+
; Data spills
@@ -312,6 +356,50 @@ define void @spill_nxv2i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1) {
ret void
}
+define void @spill_nxv8f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1) {
+; CHECK-LABEL: spill_nxv8f16
+; CHECK-DAG: st1h { z{{[01]}}.h }, p0, [sp]
+; CHECK-DAG: st1h { z{{[01]}}.h }, p0, [sp, #1, mul vl]
+ %local0 = alloca <vscale x 8 x half>
+ %local1 = alloca <vscale x 8 x half>
+ store volatile <vscale x 8 x half> %v0, <vscale x 8 x half>* %local0
+ store volatile <vscale x 8 x half> %v1, <vscale x 8 x half>* %local1
+ ret void
+}
+
+define void @spill_nxv8bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1) {
+; CHECK-LABEL: spill_nxv8bf16
+; CHECK-DAG: st1h { z{{[01]}}.h }, p0, [sp]
+; CHECK-DAG: st1h { z{{[01]}}.h }, p0, [sp, #1, mul vl]
+ %local0 = alloca <vscale x 8 x bfloat>
+ %local1 = alloca <vscale x 8 x bfloat>
+ store volatile <vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat>* %local0
+ store volatile <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat>* %local1
+ ret void
+}
+
+define void @spill_nxv4f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1) {
+; CHECK-LABEL: spill_nxv4f32
+; CHECK-DAG: st1w { z{{[01]}}.s }, p0, [sp]
+; CHECK-DAG: st1w { z{{[01]}}.s }, p0, [sp, #1, mul vl]
+ %local0 = alloca <vscale x 4 x float>
+ %local1 = alloca <vscale x 4 x float>
+ store volatile <vscale x 4 x float> %v0, <vscale x 4 x float>* %local0
+ store volatile <vscale x 4 x float> %v1, <vscale x 4 x float>* %local1
+ ret void
+}
+
+define void @spill_nxv2f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1) {
+; CHECK-LABEL: spill_nxv2f64
+; CHECK-DAG: st1d { z{{[01]}}.d }, p0, [sp]
+; CHECK-DAG: st1d { z{{[01]}}.d }, p0, [sp, #1, mul vl]
+ %local0 = alloca <vscale x 2 x double>
+ %local1 = alloca <vscale x 2 x double>
+ store volatile <vscale x 2 x double> %v0, <vscale x 2 x double>* %local0
+ store volatile <vscale x 2 x double> %v1, <vscale x 2 x double>* %local1
+ ret void
+}
+
; Predicate fills
define void @fill_nxv16i1() {
More information about the llvm-commits
mailing list