[PATCH] D82871: [SVE] Custom ISel for fixed length extract/insert_subvector.

Wed Jul 1 13:32:10 PDT 2020

paulwalker-arm marked an inline comment as done.
paulwalker-arm added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3385
+
+  case ISD::INSERT_SUBVECTOR: {
+    // Bail when not a "cast" like insert_subvector.
----------------
efriedma wrote:
> There isn't any corresponding code for INSERT_SUBVECTOR in AArch64ISelLowering?
Unlike EXTRACT_SUBVECTOR, AArch64ISelLowering didn't have any custom lowering for INSERT_SUBVECTOR for any vector types.  For this reason I assumed the defaults were fine.  My new usage when lowering fixed length to SVE only uses the legal variants so doesn't introduce any new requirements.

Repository:
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  https://reviews.llvm.org/D82871/new/

https://reviews.llvm.org/D82871