[PATCH] D79635: [RISCV] Split the pseudo instruction splitting pass

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

In D79635#2125510 <https://reviews.llvm.org/D79635#2125510>, @luismarques wrote:

> In D79635#2124242 <https://reviews.llvm.org/D79635#2124242>, @nathanchance wrote:
>
> > This patch breaks compiling the Linux kernel:
>
>
> Thanks for the detailed bug report. I have addressed this by temporarily reverting the part of this patch that wasn't NFC. This should solve the problem for now, if not please let me know.


I took a quick look and it seems that the pass "Branch Probability Basic Block Placement" (`lib/CodeGen/MachineBlockPlacement.cpp`) reorders the basic blocks.

Unfortunately some of them are referenced in pc-relative addressing. In RISC-V such addressing uses two instructions and the second one has a label to the first one (so the linker can chain to the first instruction, I assume).

After the pass we end with a wrong machine operand (the `%bb.-1` is wrong)

  $x10 = ADDI $x10, target-flags(riscv-pcrel-lo) %bb.-1

I'm not sure why this pass does not take into account such operands (or one of the analyses it uses to do the transformation), but expanding those things later seems to hide/prevent the issue. Perhaps the new basic block created in `RISCVExpandPseudo::expandAuipcInstPair` needs to be marked as `setHasAddressTaken` or something (but I have a vague recollection that this had some other consequences, I might be wrong here).


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https://reviews.llvm.org/D79635