[llvm] a61fa1a - Revert "[RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2"

[Luís Marques via llvm-commits]

Author: Luís Marques
Date: 2020-07-01T16:01:40+01:00
New Revision: a61fa1a4b9d247e34ea5541422f7040a37baf6e7

URL: https://github.com/llvm/llvm-project/commit/a61fa1a4b9d247e34ea5541422f7040a37baf6e7
DIFF: https://github.com/llvm/llvm-project/commit/a61fa1a4b9d247e34ea5541422f7040a37baf6e7.diff

LOG: Revert "[RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2"

This reverts commit 05a20a9e9aba301a828bcbd72b0ed724755752d1.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 6468319a61af..fe700ae713ba 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -168,12 +168,11 @@ bool RISCVPassConfig::addGlobalInstructionSelect() {
   return false;
 }
 
-void RISCVPassConfig::addPreSched2() { }
+void RISCVPassConfig::addPreSched2() { addPass(createRISCVExpandPseudoPass()); }
 
 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
 
 void RISCVPassConfig::addPreEmitPass2() {
-  addPass(createRISCVExpandPseudoPass());
   // Schedule the expansion of AMOs at the last possible moment, avoiding the
   // possibility for other passes to break the requirements for forward
   // progress in the LR/SC block.