[llvm] 05a20a9 - [RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2

[Luís Marques via llvm-commits]

Author: Luís Marques
Date: 2020-07-01T15:42:18+01:00
New Revision: 05a20a9e9aba301a828bcbd72b0ed724755752d1

URL: https://github.com/llvm/llvm-project/commit/05a20a9e9aba301a828bcbd72b0ed724755752d1
DIFF: https://github.com/llvm/llvm-project/commit/05a20a9e9aba301a828bcbd72b0ed724755752d1.diff

LOG: [RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2

The pass to split atomic and non-atomic RISC-V pseudo-instructions was itself
split into two passes in D79635 / commit rG2cb0644f90b7, with the splitting of
non-atomic instructions being moved to the PreSched2 phase. A comment was
added to D79635 detailing a case where this caused problems, so this commit
moves the non-atomic split pass back to the PreEmitPass2 phase. This allows
the bulk of the changes from D79635 to remain committed, while addressing the
the reported problem (the pass split is now almost NFC). Once the root problem
is fixed we can move the (non-atomic) instruction splitting pass back to
earlier in the pipeline.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index fe700ae713ba..6468319a61af 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -168,11 +168,12 @@ bool RISCVPassConfig::addGlobalInstructionSelect() {
   return false;
 }
 
-void RISCVPassConfig::addPreSched2() { addPass(createRISCVExpandPseudoPass()); }
+void RISCVPassConfig::addPreSched2() { }
 
 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
 
 void RISCVPassConfig::addPreEmitPass2() {
+  addPass(createRISCVExpandPseudoPass());
   // Schedule the expansion of AMOs at the last possible moment, avoiding the
   // possibility for other passes to break the requirements for forward
   // progress in the LR/SC block.