[PATCH] D82871: [SVE] Custom ISel for fixed length extract/insert_subvector.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3244
+// NOTE: When targeting fixed length vectors at SVE the range of MVTs is runtime
+// variable, hence this manual selection.
+static SDNode *extractSubReg(SelectionDAG *DAG, EVT VT, SDValue V) {
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I'm not sure I understand the issue here. Is the problem just that for a pattern, you need to write the type of the result?  I don't think there's any problem with writing a pattern involving a type that isn't always legal; if the type isn't legal, it just won't match.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8678
+  if (InVT.isScalableVector())
+    return Idx == 0 ? Op : SDValue();
+
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The comment here is really terse, and I'm not sure this is handling all the cases we need to.

In particular, I'm not sure this correctly handles types like nxv2f32.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82871/new/

https://reviews.llvm.org/D82871