[PATCH] D82792: [SVE][CodeGen] Legalisation of unpredicated load instructions

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin marked 5 inline comments as done.
kmclaughlin added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2379
+    auto VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
+    auto VS1 = N1->getConstantOperandAPInt(0);
+    auto VS = DAG.getVScale(DL, VT, VS0 + VS1);
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efriedma wrote:
> Is there some reason to expect the two integers have the same width?
I thought we could expect that the integers will have the same width here, since we're explicitly checking the opcodes used in the expression. I would have thought if the integers had different widths that the expression would also include a sign/zero extend or a truncate somewhere?


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:1549
+              IncrementSize));
+    MPI = LD->getPointerInfo();
+    Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, BytesIncrement);
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efriedma wrote:
> kmclaughlin wrote:
> > Where `LoVT` is not scalable we update the PointerInfo with the offset, IncrementSize. For scalable types I've just reused `LD->getPointerInfo()` for now; I'm not entirely sure how best to handle the PointerInfo for scalable vectors as MachinePointerInfo currently has no knowledge of scaled offsets.
> You can get an "empty" MachinePointerInfo.  Something like `MachinePointerInfo(LD->getPointerInfo()->getAddrSpace());`
Thanks for the suggestion on this!


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  https://reviews.llvm.org/D82792/new/

https://reviews.llvm.org/D82792