[PATCH] D82463: [AMDGPU] Spill more than wavesize CSR SGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll:31
+  %alloca = alloca i32, align 4, addrspace(5)
+  store volatile i32 0, i32 addrspace(5)* %alloca
+  call void asm sideeffect "",
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saiislam wrote:
> With this patch applied over recent trunk, I am seeing following behavior:
> 
>   - without volatile in store instruction, correct behavior (using next vgpr for spilling). stack object instruction gets optimized out
>   - with volatile in store instruction, spills are still getting overwritten
>   - With -O0, with and without volatile spills are getting overwritten.
> 
> So, whenever stack object is present, wrong behavior is getting triggered somehow.
Did you mean without the patch?


Repository:
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  https://reviews.llvm.org/D82463/new/

https://reviews.llvm.org/D82463