[llvm] 66fa313 - [ARM] Allow the usub_sat and ssub_sat intrinsics to be tail predicated
Samuel Tebbs via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 30 09:17:08 PDT 2020
Author: Samuel Tebbs
Date: 2020-06-30T17:16:58+01:00
New Revision: 66fa313999923d5e0ee08774039aac2c553112c2
URL: https://github.com/llvm/llvm-project/commit/66fa313999923d5e0ee08774039aac2c553112c2
DIFF: https://github.com/llvm/llvm-project/commit/66fa313999923d5e0ee08774039aac2c553112c2.diff
LOG: [ARM] Allow the usub_sat and ssub_sat intrinsics to be tail predicated
This patch stops the usub_sat and ssub_sat intrinsics from blocking tail predication.
Differential Revision: https://reviews.llvm.org/D82571
Added:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-sub-sat.ll
Modified:
llvm/lib/Target/ARM/MVETailPredication.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/MVETailPredication.cpp b/llvm/lib/Target/ARM/MVETailPredication.cpp
index 42a659bdf4bd..4bb60701ce5e 100644
--- a/llvm/lib/Target/ARM/MVETailPredication.cpp
+++ b/llvm/lib/Target/ARM/MVETailPredication.cpp
@@ -245,6 +245,8 @@ bool MVETailPredication::IsPredicatedVectorLoop() {
LLVM_FALLTHROUGH;
case Intrinsic::sadd_sat:
case Intrinsic::uadd_sat:
+ case Intrinsic::ssub_sat:
+ case Intrinsic::usub_sat:
continue;
case Intrinsic::fma:
case Intrinsic::trunc:
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-sub-sat.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-sub-sat.ll
new file mode 100644
index 000000000000..790311a54aa1
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-sub-sat.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs -disable-mve-tail-predication=false -o - %s | FileCheck %s
+define arm_aapcs_vfpcc void @usub_sat(i16* noalias nocapture readonly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
+; CHECK-LABEL: usub_sat:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: popeq {r7, pc}
+; CHECK-NEXT: dlstp.16 lr, r3
+; CHECK-NEXT: .LBB0_1: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vldrh.u16 q0, [r1], #16
+; CHECK-NEXT: vldrh.u16 q1, [r0], #16
+; CHECK-NEXT: vqsub.u16 q0, q1, q0
+; CHECK-NEXT: vstrh.16 q0, [r2], #16
+; CHECK-NEXT: letp lr, .LBB0_1
+; CHECK-NEXT: @ %bb.2: @ %while.end
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ %cmp7 = icmp eq i32 %blockSize, 0
+ br i1 %cmp7, label %while.end, label %vector.ph
+
+vector.ph: ; preds = %entry
+ %n.rnd.up = add i32 %blockSize, 7
+ %n.vec = and i32 %n.rnd.up, -8
+ %trip.count.minus.1 = add i32 %blockSize, -1
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %next.gep = getelementptr i16, i16* %pSrcA, i32 %index
+ %next.gep20 = getelementptr i16, i16* %pDst, i32 %index
+ %next.gep21 = getelementptr i16, i16* %pSrcB, i32 %index
+ %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %trip.count.minus.1)
+ %0 = bitcast i16* %next.gep to <8 x i16>*
+ %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
+ %1 = bitcast i16* %next.gep21 to <8 x i16>*
+ %wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
+ %2 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24)
+ %3 = bitcast i16* %next.gep20 to <8 x i16>*
+ call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
+ %index.next = add i32 %index, 8
+ %4 = icmp eq i32 %index.next, %n.vec
+ br i1 %4, label %while.end, label %vector.body
+
+while.end: ; preds = %vector.body, %entry
+ ret void
+}
+
+define arm_aapcs_vfpcc void @ssub_sat(i16* noalias nocapture readonly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
+; CHECK-LABEL: ssub_sat:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: popeq {r7, pc}
+; CHECK-NEXT: dlstp.16 lr, r3
+; CHECK-NEXT: .LBB1_1: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vldrh.u16 q0, [r1], #16
+; CHECK-NEXT: vldrh.u16 q1, [r0], #16
+; CHECK-NEXT: vqsub.s16 q0, q1, q0
+; CHECK-NEXT: vstrh.16 q0, [r2], #16
+; CHECK-NEXT: letp lr, .LBB1_1
+; CHECK-NEXT: @ %bb.2: @ %while.end
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ %cmp7 = icmp eq i32 %blockSize, 0
+ br i1 %cmp7, label %while.end, label %vector.ph
+
+vector.ph: ; preds = %entry
+ %n.rnd.up = add i32 %blockSize, 7
+ %n.vec = and i32 %n.rnd.up, -8
+ %trip.count.minus.1 = add i32 %blockSize, -1
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %next.gep = getelementptr i16, i16* %pSrcA, i32 %index
+ %next.gep20 = getelementptr i16, i16* %pDst, i32 %index
+ %next.gep21 = getelementptr i16, i16* %pSrcB, i32 %index
+ %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %trip.count.minus.1)
+ %0 = bitcast i16* %next.gep to <8 x i16>*
+ %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
+ %1 = bitcast i16* %next.gep21 to <8 x i16>*
+ %wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
+ %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24)
+ %3 = bitcast i16* %next.gep20 to <8 x i16>*
+ call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
+ %index.next = add i32 %index, 8
+ %4 = icmp eq i32 %index.next, %n.vec
+ br i1 %4, label %while.end, label %vector.body
+
+while.end: ; preds = %vector.body, %entry
+ ret void
+}
+
+declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
+
+declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
+
+declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
+
+declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
+
+declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
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