[PATCH] D82463: [AMDGPU] Spill more than wavesize CSR SGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll:10
+define void @spill_more_than_wavesize_csr_sgprs() {
+  call void asm sideeffect "",
+   "~{s35},~{s36},~{s37},~{s38},~{s39},~{s40},~{s41},~{s42}
----------------
kerbowa wrote:
> kerbowa wrote:
> > arsenm wrote:
> > > You removed the stack object, but my point was without your patch, this already works:
> > > 
> > > 	v_writelane_b32 v0, s98, 63
> > > 	v_writelane_b32 v1, s99, 0
> > > 	v_writelane_b32 v1, s100, 1
> > > 
> > > So that means this test should include with and without the stack object. We also need to solve the mystery of why this stack object is needed
> > Without the stack object FuncInfo->VGPRReservedForSGPRSpill is 0.
> No VGPR is pre-reserved when there are no stack objects.
> https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/AMDGPU/SIISelLowering.cpp#L11283
> 
> This patch will fix some current Navi issues as well where it's more common to run out of lanes in the pre-reserved register.
This doesn't really make sense though; why would this be a factor in the reservation logic?


Repository:
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https://reviews.llvm.org/D82463