[llvm] ab27603 - [DSE, MSSA] Add missing -enable-dse-memoryssa flag to test.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2020-06-24T14:07:30+01:00
New Revision: ab27603c6d444b15e5f8efc090611488440211a9

URL: https://github.com/llvm/llvm-project/commit/ab27603c6d444b15e5f8efc090611488440211a9
DIFF: https://github.com/llvm/llvm-project/commit/ab27603c6d444b15e5f8efc090611488440211a9.diff

LOG: [DSE,MSSA] Add missing -enable-dse-memoryssa flag to test.

Added: 
    

Modified: 
    llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll
index e30fa2e7777c..6cd77a59df6b 100644
--- a/llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll
+++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -dse -enable-dse-partial-store-merging=false < %s | FileCheck %s
+; RUN: opt -S -dse -enable-dse-memoryssa -enable-dse-partial-store-merging=false < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-bgq-linux"
 
@@ -252,6 +252,7 @@ define signext i8 @test5(i32 *%ptr) {
 ; CHECK-NEXT:    [[BPTR:%.*]] = bitcast i32* [[PTR:%.*]] to i8*
 ; CHECK-NEXT:    [[BPTR1:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 1
 ; CHECK-NEXT:    [[BPTR2:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 2
+; CHECK-NEXT:    [[BPTR3:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 3
 ; CHECK-NEXT:    [[WPTR:%.*]] = bitcast i8* [[BPTR]] to i16*
 ; CHECK-NEXT:    [[WPTR1:%.*]] = bitcast i8* [[BPTR1]] to i16*
 ; CHECK-NEXT:    [[WPTR2:%.*]] = bitcast i8* [[BPTR2]] to i16*