[llvm] cf23852 - [Target] As part of using inclusive language within the llvm project,

Hubert Tong via llvm-commits llvm-commits at lists.llvm.org
Sat Jun 20 12:53:18 PDT 2020


On Sat, Jun 20, 2020 at 3:29 PM Eric Christopher via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

>
> Author: Eric Christopher
> Date: 2020-06-20T00:06:39-07:00
> New Revision: cf23852587144e3014e72bb5b6993ae21f6a09be
>
> URL:
> https://github.com/llvm/llvm-project/commit/cf23852587144e3014e72bb5b6993ae21f6a09be
> DIFF:
> https://github.com/llvm/llvm-project/commit/cf23852587144e3014e72bb5b6993ae21f6a09be.diff
>
> LOG: [Target] As part of using inclusive language within the llvm project,
> migrate away from the use of blacklist and whitelist.
>
> This change affects an internal llvm command line option.
>
> Added:
>     llvm/test/CodeGen/WebAssembly/lower-em-exceptions-allowed.ll
>
> Modified:
>     llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
>     llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
>     llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
>     llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
>     llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
>     llvm/lib/Target/ARM/ARMTargetTransformInfo.h
>     llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
>     llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
>     llvm/lib/Target/X86/X86ISelLowering.cpp
>
> Removed:
>     llvm/test/CodeGen/WebAssembly/lower-em-exceptions-whitelist.ll
>
>
>
> ################################################################################
> diff  --git a/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
> b/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
> index 5b1ebde8b77c..d5b016728c71 100644
> --- a/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
> +++ b/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
> @@ -1336,9 +1336,7 @@ unsigned DWARFVerifier::verifyNameIndexCompleteness(
>    // "The name index must contain an entry for each debugging information
> entry
>    // that defines a named subprogram, label, variable, type, or namespace,
>    // subject to ..."
> -  // Instead whitelisting all TAGs representing a "type" or a
> "subprogram", to
> -  // make sure we catch any missing items, we instead blacklist all TAGs
> that we
> -  // know shouldn't be indexed.
> +  // Explicitly exclude all TAGs that we know shouldn't be indexed.
>    switch (Die.getTag()) {
>    // Compile units and modules have names but shouldn't be indexed.
>    case DW_TAG_compile_unit:
>
> diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
> b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
> index f9c6a6c51335..5139ae5ccaf1 100644
> --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
> +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
> @@ -6408,7 +6408,7 @@
> AArch64InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,
>
>      // If we don't know anything about the callee, assume it depends on
> the
>      // stack layout of the caller. In that case, it's only legal to
> outline
> -    // as a tail-call.  Whitelist the call instructions we know about so
> we
> +    // as a tail-call. Explicitly list the call instructions we know
> about so we
>      // don't get unexpected results with call pseudo-instructions.
>      auto UnknownCallOutlineType = outliner::InstrType::Illegal;
>      if (MI.getOpcode() == AArch64::BLR ||
>
> diff  --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
> b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
> index 0e6a444b2751..68d0012e3314 100644
> --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
> +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
> @@ -933,7 +933,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const
> GCNSubtarget &ST_,
>      const bool IsStore = Op == G_STORE;
>
>      auto &Actions = getActionDefinitionsBuilder(Op);
> -    // Whitelist some common cases.
> +    // Explicitly list some common cases.
>      // TODO: Does this help compile time at all?
>      Actions.legalForTypesWithMemDesc({{S32, GlobalPtr, 32, GlobalAlign32},
>                                        {V2S32, GlobalPtr, 64,
> GlobalAlign32},
>
> diff  --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
> b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
> index 66334d1b22ce..504d0cc4c08a 100644
> --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
> +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
> @@ -5912,8 +5912,8 @@
> ARMBaseInstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,
>    if (MI.isCall()) {
>      // If we don't know anything about the callee, assume it depends on
> the
>      // stack layout of the caller. In that case, it's only legal to
> outline
> -    // as a tail-call.  Whitelist the call instructions we know about so
> we
> -    // don't get unexpected results with call pseudo-instructions.
> +    // as a tail-call. Explicitly list the call instructions we know
> about so
> +    // we don't get unexpected results with call pseudo-instructions.
>      auto UnknownCallOutlineType = outliner::InstrType::Illegal;
>      if (Opc == ARM::BL || Opc == ARM::tBL || Opc == ARM::BLX ||
>          Opc == ARM::tBLXr || Opc == ARM::tBLXi)
>
> diff  --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
> b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
> index 82849dc67f43..680f239c752c 100644
> --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
> +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
> @@ -57,13 +57,13 @@ bool ARMTTIImpl::areInlineCompatible(const Function
> *Caller,
>    const FeatureBitset &CalleeBits =
>        TM.getSubtargetImpl(*Callee)->getFeatureBits();
>
> -  // To inline a callee, all features not in the whitelist must match
> exactly.
> -  bool MatchExact = (CallerBits & ~InlineFeatureWhitelist) ==
> -                    (CalleeBits & ~InlineFeatureWhitelist);
> -  // For features in the whitelist, the callee's features must be a
> subset of
> +  // To inline a callee, all features not in the allowed list must match
> exactly.
> +  bool MatchExact = (CallerBits & ~InlineFeaturesAllowed) ==
> +                    (CalleeBits & ~InlineFeaturesAllowed);
> +  // For features in the allowed list, the callee's features must be a
> subset of
>    // the callers'.
> -  bool MatchSubset = ((CallerBits & CalleeBits) & InlineFeatureWhitelist)
> ==
> -                     (CalleeBits & InlineFeatureWhitelist);
> +  bool MatchSubset = ((CallerBits & CalleeBits) & InlineFeaturesAllowed)
> ==
> +                     (CalleeBits & InlineFeaturesAllowed);
>    return MatchExact && MatchSubset;
>  }
>
>
> diff  --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
> b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
> index d319aa88c714..7a2db740f185 100644
> --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
> +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
> @@ -47,13 +47,13 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl>
> {
>    const ARMSubtarget *ST;
>    const ARMTargetLowering *TLI;
>
> -  // Currently the following features are excluded from
> InlineFeatureWhitelist.
> +  // Currently the following features are excluded from
> InlineFeaturesAllowed.
>    // ModeThumb, FeatureNoARM, ModeSoftFloat, FeatureFP64, FeatureD32
>    // Depending on whether they are set or unset,
> diff erent
>    // instructions/registers are available. For example, inlining a callee
> with
>    // -thumb-mode in a caller with +thumb-mode, may cause the assembler to
>    // fail if the callee uses ARM only instructions, e.g. in inline asm.
> -  const FeatureBitset InlineFeatureWhitelist = {
> +  const FeatureBitset InlineFeaturesAllowed = {
>        ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON,
> ARM::FeatureThumb2,
>        ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
>        ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
>
> diff  --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
> b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
> index 4eaa8102101d..a4ff01015312 100644
> --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
> +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
> @@ -54,7 +54,7 @@ ARMELFObjectWriter::ARMELFObjectWriter(uint8_t OSABI)
>  bool ARMELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym,
>                                                   unsigned Type) const {
>    // FIXME: This is extremely conservative. This really needs to use a
>
s/a/an/;


> -  // whitelist with a clear explanation for why each realocation needs to
> +  // explicit list with a clear explanation for why each realocation
> needs to
>    // point to the symbol, not to the section.
>    switch (Type) {
>    default:
>
> diff  --git
> a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
> b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
> index 96a3e9a9d2fe..5fce4a600510 100644
> --- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
> +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
> @@ -221,10 +221,10 @@ using namespace llvm;
>  #define DEBUG_TYPE "wasm-lower-em-ehsjlj"
>
>  static cl::list<std::string>
> -    EHWhitelist("emscripten-cxx-exceptions-whitelist",
> +    EHAllowlist("emscripten-cxx-exceptions-allowed",
>                  cl::desc("The list of function names in which
> Emscripten-style "
>                           "exception handling is enabled (see emscripten "
> -                         "EMSCRIPTEN_CATCHING_WHITELIST options)"),
> +                         "EMSCRIPTEN_CATCHING_ALLOWED options)"),
>                  cl::CommaSeparated);
>
>  namespace {
> @@ -248,8 +248,8 @@ class WebAssemblyLowerEmscriptenEHSjLj final : public
> ModulePass {
>    DenseMap<int, Function *> FindMatchingCatches;
>    // Map of <function signature string, invoke_ wrappers>
>    StringMap<Function *> InvokeWrappers;
> -  // Set of whitelisted function names for exception handling
> -  std::set<std::string> EHWhitelistSet;
> +  // Set of allowed function names for exception handling
> +  std::set<std::string> EHAllowlistSet;
>
>    StringRef getPassName() const override {
>      return "WebAssembly Lower Emscripten Exceptions";
> @@ -265,7 +265,7 @@ class WebAssemblyLowerEmscriptenEHSjLj final : public
> ModulePass {
>                        Value *&LongjmpResult, BasicBlock *&EndBB);
>    Function *getInvokeWrapper(CallBase *CI);
>
> -  bool areAllExceptionsAllowed() const { return EHWhitelistSet.empty(); }
> +  bool areAllExceptionsAllowed() const { return EHAllowlistSet.empty(); }
>    bool canLongjmp(Module &M, const Value *Callee) const;
>    bool isEmAsmCall(Module &M, const Value *Callee) const;
>
> @@ -276,7 +276,7 @@ class WebAssemblyLowerEmscriptenEHSjLj final : public
> ModulePass {
>
>    WebAssemblyLowerEmscriptenEHSjLj(bool EnableEH = true, bool EnableSjLj
> = true)
>        : ModulePass(ID), EnableEH(EnableEH), EnableSjLj(EnableSjLj) {
> -    EHWhitelistSet.insert(EHWhitelist.begin(), EHWhitelist.end());
> +    EHAllowlistSet.insert(EHAllowlist.begin(), EHAllowlist.end());
>    }
>    bool runOnModule(Module &M) override;
>
> @@ -746,7 +746,7 @@ bool
> WebAssemblyLowerEmscriptenEHSjLj::runEHOnFunction(Function &F) {
>    SmallVector<Instruction *, 64> ToErase;
>    SmallPtrSet<LandingPadInst *, 32> LandingPads;
>    bool AllowExceptions = areAllExceptionsAllowed() ||
> -                         EHWhitelistSet.count(std::string(F.getName()));
> +                         EHAllowlistSet.count(std::string(F.getName()));
>
>    for (BasicBlock &BB : F) {
>      auto *II = dyn_cast<InvokeInst>(BB.getTerminator());
>
> diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
> b/llvm/lib/Target/X86/X86ISelLowering.cpp
> index e2a9231065e0..c5debd6ef7a8 100644
> --- a/llvm/lib/Target/X86/X86ISelLowering.cpp
> +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
> @@ -23087,7 +23087,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op,
> SelectionDAG &DAG) const {
>        Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() ==
> ISD::TRUNCATE) {
>      SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
>      if (T1.getValueType() == T2.getValueType() &&
> -        // Blacklist CopyFromReg to avoid partial register stalls.
> +        // Exclude CopyFromReg to avoid partial register stalls.
>          T1.getOpcode() != ISD::CopyFromReg &&
> T2.getOpcode()!=ISD::CopyFromReg){
>        SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, T1.getValueType(), T2,
> T1,
>                                   CC, Cond);
>
> diff  --git
> a/llvm/test/CodeGen/WebAssembly/lower-em-exceptions-whitelist.ll
> b/llvm/test/CodeGen/WebAssembly/lower-em-exceptions-allowed.ll
> similarity index 98%
> rename from llvm/test/CodeGen/WebAssembly/lower-em-exceptions-whitelist.ll
> rename to llvm/test/CodeGen/WebAssembly/lower-em-exceptions-allowed.ll
> index ce33a9f4b455..de6d2205e31c 100644
> --- a/llvm/test/CodeGen/WebAssembly/lower-em-exceptions-whitelist.ll
> +++ b/llvm/test/CodeGen/WebAssembly/lower-em-exceptions-allowed.ll
> @@ -1,4 +1,4 @@
> -; RUN: opt < %s -wasm-lower-em-ehsjlj
> -emscripten-cxx-exceptions-whitelist=do_catch -S | FileCheck %s
> +; RUN: opt < %s -wasm-lower-em-ehsjlj
> -emscripten-cxx-exceptions-allowed=do_catch -S | FileCheck %s
>
>  target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
>  target triple = "wasm32-unknown-unknown"
>
>
>
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