[PATCH] D82234: [amdgpu] Fix REL32 relocations with negative offsets.

[Michael Liao via Phabricator via llvm-commits]

hliao added a comment.

This patch only handles the case where that offset is representable in a 32-bit signed integer. For a  generic 64-bit offset out of range of 32-bit integer, we need to revise the relocation spec to enhance REL32_HI from the orginal

  (S +A - P) >> 32

to

  (S + (A << 32) - P) >> 32

where A is that 32-bit sword addend. In fact, we split a 64-bit offset into low 32-bit addend used in REL32_LO and high 32-bit addend used in REL32_HI. However, that needs changes in more than components. As that's the rate case,  I want to address the current critical issue first and will start the discussion on relocation changes.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D82234/new/

https://reviews.llvm.org/D82234