[llvm] 7c93a19 - NFC: Remove disabled rule from postlegalizer-combiner-zip.mir test

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2020-06-15T13:15:02-07:00
New Revision: 7c93a19790c499b882871b4cf432c28c43ccb1ae

URL: https://github.com/llvm/llvm-project/commit/7c93a19790c499b882871b4cf432c28c43ccb1ae
DIFF: https://github.com/llvm/llvm-project/commit/7c93a19790c499b882871b4cf432c28c43ccb1ae.diff

LOG: NFC: Remove disabled rule from postlegalizer-combiner-zip.mir test

Apparently an x86 bot doesn't like the disabled rule in this test.

http://lab.llvm.org:8011/builders/fuchsia-x86_64-linux/builds/6569

Remove disabled rule and update the test to try and pacify the bot.

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-zip.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-zip.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-zip.mir
index 3d71b6a948dc..9484ee2bf702 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-zip.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-zip.mir
@@ -3,7 +3,7 @@
 # Check that we can recognize a shuffle mask for a zip instruction, and produce
 # G_ZIP1 or G_ZIP2 where appropriate.
 #
-# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner --aarch64postlegalizercombinerhelper-disable-rule=ext -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
 
 ...
 ---
@@ -160,8 +160,9 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
-    ; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[COPY1]], shufflemask(1, 2)
-    ; CHECK: $q0 = COPY [[SHUF]](<2 x s64>)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[EXT:%[0-9]+]]:_(<2 x s64>) = G_EXT [[COPY]], [[COPY1]], [[C]](s32)
+    ; CHECK: $q0 = COPY [[EXT]](<2 x s64>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(<2 x s64>) = COPY $q0
     %1:_(<2 x s64>) = COPY $q1
@@ -186,8 +187,9 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
-    ; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[COPY1]], shufflemask(0, 1)
-    ; CHECK: $q0 = COPY [[SHUF]](<2 x s64>)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[EXT:%[0-9]+]]:_(<2 x s64>) = G_EXT [[COPY]], [[COPY1]], [[C]](s32)
+    ; CHECK: $q0 = COPY [[EXT]](<2 x s64>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(<2 x s64>) = COPY $q0
     %1:_(<2 x s64>) = COPY $q1