[PATCH] D81524: AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads

[Matt Arsenault via Phabricator via llvm-commits]

arsenm closed this revision.
arsenm marked 2 inline comments as done.
arsenm added a comment.

2ca552322c29b61e8c20a0b31cf452de88d8af1c <https://reviews.llvm.org/rG2ca552322c29b61e8c20a0b31cf452de88d8af1c>



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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:1127-1128
+
+  LLT EltTy = Ty.getElementType();
+  return LLT::vector(128 / EltTy.getSizeInBits(), EltTy);
+}
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foad wrote:
> Perhaps assert that EltTy is a power of 2 size (or equivalently that the divsion `128 / EltTy.getSizeInBits()` is exact) to guard against being called with weird types like v1s96 or v2s48?
Thankfully 1 element vectors don't exist in globalisel, but I would expect this to handle v2s48 (although one should never reach here I guess)


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