[PATCH] D81685: BypassSlowDivision: Fix dropping debug info

[Vedant Kumar via Phabricator via llvm-commits]

vsk added inline comments.


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Comment at: llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll:29
+; FIXME: The debugloc for the rem parts end up with the dbg of the
+; division.
+define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
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arsenm wrote:
> vsk wrote:
> > I think this is good? At least, it seems better than having the source location of the srem (!10) appear in the fast block.
> I would hope the rem would get the location of the original rem, but I guess this is better than nothing (especially for architectures where these will end up merging into SDIVREM/UDIVREM later anyway)
One issue with using the location of the original rem is that single-stepping would look like 'line 3 -> line 4 -> line 3'. It's unfortunate to lose the unique breakpoint location for the rem, but if there were a second rem that used the cached value, this would happen anyway.


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  https://reviews.llvm.org/D81685/new/

https://reviews.llvm.org/D81685