[llvm] a5a0015 - [X86] Add non-uniform vector signbit test cases

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-06-12T14:58:15+01:00
New Revision: a5a00155a200f4b1fa0200a090723d8fa0c2b688

URL: https://github.com/llvm/llvm-project/commit/a5a00155a200f4b1fa0200a090723d8fa0c2b688
DIFF: https://github.com/llvm/llvm-project/commit/a5a00155a200f4b1fa0200a090723d8fa0c2b688.diff

LOG: [X86] Add non-uniform vector signbit test cases

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/signbit-shift.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/signbit-shift.ll b/llvm/test/CodeGen/X86/signbit-shift.ll
index 94d68ccc84bd..50342ee9e598 100644
--- a/llvm/test/CodeGen/X86/signbit-shift.ll
+++ b/llvm/test/CodeGen/X86/signbit-shift.ll
@@ -43,6 +43,21 @@ define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define <4 x i32> @add_zext_ifpos_vec_nonsplat(<4 x i32> %x) {
+; CHECK-LABEL: add_zext_ifpos_vec_nonsplat:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcmpeqd %xmm1, %xmm1
+; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
+; CHECK-NEXT:    movdqa {{.*#+}} xmm1 = [42,43,44,45]
+; CHECK-NEXT:    psubd %xmm0, %xmm1
+; CHECK-NEXT:    movdqa %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %e = zext <4 x i1> %c to <4 x i32>
+  %r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>
+  ret <4 x i32> %r
+}
+
 define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       # %bb.0:
@@ -93,6 +108,19 @@ define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define <4 x i32> @add_sext_ifpos_vec_nonsplat(<4 x i32> %x) {
+; CHECK-LABEL: add_sext_ifpos_vec_nonsplat:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcmpeqd %xmm1, %xmm1
+; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
+; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %e = sext <4 x i1> %c to <4 x i32>
+  %r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>
+  ret <4 x i32> %r
+}
+
 define i32 @sel_ifpos_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_fval_bigger:
 ; CHECK:       # %bb.0:
@@ -204,6 +232,20 @@ define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define <4 x i32> @add_lshr_not_vec_nonsplat(<4 x i32> %x) {
+; CHECK-LABEL: add_lshr_not_vec_nonsplat:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcmpeqd %xmm1, %xmm1
+; CHECK-NEXT:    pxor %xmm1, %xmm0
+; CHECK-NEXT:    psrld $31, %xmm0
+; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
+  %r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>
+  ret <4 x i32> %r
+}
+
 define i32 @sub_lshr_not(i32 %x) {
 ; CHECK-LABEL: sub_lshr_not:
 ; CHECK:       # %bb.0:
@@ -229,6 +271,20 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define <4 x i32> @sub_lshr_not_vec_nonsplat(<4 x i32> %x) {
+; CHECK-LABEL: sub_lshr_not_vec_nonsplat:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcmpeqd %xmm1, %xmm1
+; CHECK-NEXT:    pxor %xmm1, %xmm0
+; CHECK-NEXT:    psrad $31, %xmm0
+; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
+  %r = sub <4 x i32> <i32 42, i32 43, i32 44, i32 45>, %e
+  ret <4 x i32> %r
+}
+
 define i32 @sub_lshr(i32 %x, i32 %y) {
 ; CHECK-LABEL: sub_lshr:
 ; CHECK:       # %bb.0:
@@ -265,8 +321,8 @@ define i32 @sub_const_op_lshr(i32 %x) {
   ret i32 %r
 }
 
-define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
-; CHECK-LABEL: sub_const_op_lshr_vec:
+define <4 x i32> @sub_const_op_lshr_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: sub_const_op_lshr_vec_splat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    psrad $31, %xmm0
 ; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
@@ -276,3 +332,14 @@ define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define <4 x i32> @sub_const_op_lshr_vec_nonsplat(<4 x i32> %x) {
+; CHECK-LABEL: sub_const_op_lshr_vec_nonsplat:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    psrad $31, %xmm0
+; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+  %r = sub <4 x i32> <i32 42, i32 43, i32 44, i32 45>, %sh
+  ret <4 x i32> %r
+}
+