[PATCH] D81724: [MVT] Add new MVT types for RISC-V vector.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
HsiangKai added reviewers: rogfer01, evandro, rkruppe.
Herald added subscribers: luismarques, sameer.abuasal, s.egerton, lenary, Jim, PkmX, shiva0217, kito-cheng, simoncook, aheejin, hiraditya, dschuff.
Herald added a project: LLVM.

In RISC-V vector extension, users could group multiple vector registers as one pseudo register. In mixed width operations, users could use partial vector registers to reduce the register pressure. The parameter to control register grouping and partial use is called LMUL. LMUL is a part of the type. So, we have a bunch of vector types. In order to support all these types, we need new MVT types in LLVM. In this patch, I added several MVT types that are used in RISC-V vector implementation. This is a standalone patch for MVT types without RISC-V related implementation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81724

Files:
  llvm/include/llvm/CodeGen/ValueTypes.td
  llvm/include/llvm/Support/MachineValueType.h
  llvm/lib/CodeGen/ValueTypes.cpp
  llvm/lib/IR/Function.cpp
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/IntrinsicEmitter.cpp

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