[PATCH] D81675: SILoadStoreOptimizer: add support for GFX10 image instructions

Thu Jun 11 12:07:56 PDT 2020

rampitec added inline comments.

================
Comment at: llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:116

+// GFX10 image_sample instructions can have 16 vaddrs + 1 srsrc + 1 ssamp.
+const unsigned MAX_ADDRESS_REGS = 18;
----------------
foad wrote:
> Is this really true? I see opcodes like IMAGE_SAMPLE_D_CL_O_V4_V16 mentioned in some generated tables, but I'm not sure what the V16 there really means or whether these will ever occur in practice.
I think that's because we do not have all register classes, so it uses VReg_512 for 10, 11, or 12 dword address for example. I believe a longest one has 12 vaddrs, like this:

```
image_sample_c_d_cl_o v[16:19], [v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x16,0x0f,0xec,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x00]
0x16,0x0f,0xec,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14
```

You can check it in MIMGInstructions.td where MIMG_Sampler_AddrSizes is defined.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81675/new/

https://reviews.llvm.org/D81675