[PATCH] D81675: SILoadStoreOptimizer: add support for GFX10 image instructions

Thu Jun 11 11:32:58 PDT 2020

foad created this revision.
foad added reviewers: piotr, arsenm, rampitec, nhaehnle.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, wdng, jvesely.
Herald added a project: LLVM.
foad marked 2 inline comments as done.
foad added a comment.

This isn't ready to push yet but I'd like to get some feedback on it -- see comments inline.

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Comment at: llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:116

+// GFX10 image_sample instructions can have 16 vaddrs + 1 srsrc + 1 ssamp.
+const unsigned MAX_ADDRESS_REGS = 18;
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Is this really true? I see opcodes like IMAGE_SAMPLE_D_CL_O_V4_V16 mentioned in some generated tables, but I'm not sure what the V16 there really means or whether these will ever occur in practice.

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Comment at: llvm/test/CodeGen/AMDGPU/merge-image-load.mir:2
 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX9 %s

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These tests pass with -mcpu=gfx1010 but I don't think they're really testing anything useful. Do I need to regenerate them using gfx10-specific image sample opcodes or something?

GFX10 image instructions use one or more address operands starting at
vaddr0, instead of a single vaddr operand, to allow for NSA forms.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81675

Files:
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/test/CodeGen/AMDGPU/merge-image-load.mir
  llvm/test/CodeGen/AMDGPU/merge-image-sample.mir

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