[PATCH] D81638: AMDGPU/GlobalISel: Fix 96-bit local loads

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Other than on SI, there are 96-bit DS read/write. Is this just working around some later selection problem?



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:275
   case 96:
-    if (!ST.hasDwordx3LoadStores())
+    if (!ST.hasDwordx3LoadStores() || AS == AMDGPUAS::LOCAL_ADDRESS)
       return false;
----------------
The address space doesn't make this special? This willl break SI?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81638/new/

https://reviews.llvm.org/D81638