[PATCH] D81648: MIR Statepoint refactoring. Part 4: ISEL changes.

[Denis Antrushin via Phabricator via llvm-commits]

dantrushin created this revision.
dantrushin added reviewers: reames, skatkov, bogner.
Herald added subscribers: llvm-commits, hiraditya, MatzeB.
Herald added a project: LLVM.

Implement variadic-def statepoint lowering.
Due to SDNode space limitation we use simple scheme: just assign first
N derived pointers to VRegs, passing others on stack slot, as in old
implementation. For that we must ensure that these `N` first pointers
are not constant or other non-relocatable objects, so we sort derived
pointers before lowering them.
New statepoint looks like this:

  reloc1,reloc2,... = STATEPOINT ..., derived1<tied-def0>, derived2<tied-def1>, ...

`N` is further limited my maximal number of tied registers machine
instruction can have (15 at the moment).

Full change set is available at D81603 <https://reviews.llvm.org/D81603>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81648

Files:
  llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
  llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/test/CodeGen/X86/statepoint-call-lowering.ll
  llvm/test/CodeGen/X86/statepoint-duplicates-export.ll
  llvm/test/CodeGen/X86/statepoint-invoke.ll
  llvm/test/CodeGen/X86/statepoint-no-extra-const.ll
  llvm/test/CodeGen/X86/statepoint-regs.ll
  llvm/test/CodeGen/X86/statepoint-uniqueing.ll

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