[llvm] 324e136 - [X86] Split imm handling out of selectMOV64Imm32 and add a separate isel pattern.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 10 11:13:19 PDT 2020
Author: Craig Topper
Date: 2020-06-10T11:12:36-07:00
New Revision: 324e13668e561c83c53cd08b78b66e2f83146a7b
URL: https://github.com/llvm/llvm-project/commit/324e13668e561c83c53cd08b78b66e2f83146a7b
DIFF: https://github.com/llvm/llvm-project/commit/324e13668e561c83c53cd08b78b66e2f83146a7b.diff
LOG: [X86] Split imm handling out of selectMOV64Imm32 and add a separate isel pattern.
This makes the pattern available to global isel.
Added:
Modified:
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/test/CodeGen/X86/GlobalISel/constant.ll
llvm/test/CodeGen/X86/GlobalISel/ptr-add.ll
llvm/test/CodeGen/X86/GlobalISel/select-constant.mir
llvm/test/CodeGen/X86/GlobalISel/select-ptr-add.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index fadcb173cd4b..ee2c5246fd0d 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2479,15 +2479,6 @@ bool X86DAGToDAGISel::selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
}
bool X86DAGToDAGISel::selectMOV64Imm32(SDValue N, SDValue &Imm) {
- if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
- uint64_t ImmVal = CN->getZExtValue();
- if (!isUInt<32>(ImmVal))
- return false;
-
- Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i64);
- return true;
- }
-
// In static codegen with small code model, we can get the address of a label
// into a register with 'movl'
if (N->getOpcode() != X86ISD::Wrapper)
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index f0400cbe7ff5..a5333ece2c93 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -318,15 +318,14 @@ def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",
// Materialize i64 constant where top 32-bits are zero. This could theoretically
// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
// that would make it more
diff icult to rematerialize.
-let isReMaterializable = 1, isAsCheapAsAMove = 1,
- isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in
-def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "", []>;
-
-// This 64-bit pseudo-move can be used for both a 64-bit constant that is
-// actually the zero-extension of a 32-bit constant and for labels in the
-// x86-64 small code model.
-def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>;
-
+let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
+ isPseudo = 1, SchedRW = [WriteMove] in
+def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "",
+ [(set GR64:$dst, i64immZExt32:$src)]>;
+
+// This 64-bit pseudo-move can also be used for labels in the x86-64 small code
+// model.
+def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [X86Wrapper]>;
def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>;
// Use sbb to materialize carry bit.
diff --git a/llvm/test/CodeGen/X86/GlobalISel/constant.ll b/llvm/test/CodeGen/X86/GlobalISel/constant.ll
index f6ebb70fcf50..479ac84239d8 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/constant.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/constant.ll
@@ -37,7 +37,7 @@ define i64 @const_i64() {
define i64 @const_i64_u32() {
; ALL-LABEL: const_i64_u32:
; ALL: # %bb.0:
-; ALL-NEXT: movq $1879048192, %rax # imm = 0x70000000
+; ALL-NEXT: movl $1879048192, %eax # imm = 0x70000000
; ALL-NEXT: retq
ret i64 1879048192
}
diff --git a/llvm/test/CodeGen/X86/GlobalISel/ptr-add.ll b/llvm/test/CodeGen/X86/GlobalISel/ptr-add.ll
index db757a51ebe8..99689df2f371 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/ptr-add.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/ptr-add.ll
@@ -25,7 +25,7 @@ define i32* @test_gep_i8(i32 *%arr, i8 %ind) {
define i32* @test_gep_i8_const(i32 *%arr) {
; X64_GISEL-LABEL: test_gep_i8_const:
; X64_GISEL: # %bb.0:
-; X64_GISEL-NEXT: movq $80, %rax
+; X64_GISEL-NEXT: movl $80, %eax
; X64_GISEL-NEXT: addq %rdi, %rax
; X64_GISEL-NEXT: retq
;
@@ -60,7 +60,7 @@ define i32* @test_gep_i16(i32 *%arr, i16 %ind) {
define i32* @test_gep_i16_const(i32 *%arr) {
; X64_GISEL-LABEL: test_gep_i16_const:
; X64_GISEL: # %bb.0:
-; X64_GISEL-NEXT: movq $80, %rax
+; X64_GISEL-NEXT: movl $80, %eax
; X64_GISEL-NEXT: addq %rdi, %rax
; X64_GISEL-NEXT: retq
;
@@ -92,7 +92,7 @@ define i32* @test_gep_i32(i32 *%arr, i32 %ind) {
define i32* @test_gep_i32_const(i32 *%arr) {
; X64_GISEL-LABEL: test_gep_i32_const:
; X64_GISEL: # %bb.0:
-; X64_GISEL-NEXT: movq $20, %rax
+; X64_GISEL-NEXT: movl $20, %eax
; X64_GISEL-NEXT: addq %rdi, %rax
; X64_GISEL-NEXT: retq
;
@@ -122,7 +122,7 @@ define i32* @test_gep_i64(i32 *%arr, i64 %ind) {
define i32* @test_gep_i64_const(i32 *%arr) {
; X64_GISEL-LABEL: test_gep_i64_const:
; X64_GISEL: # %bb.0:
-; X64_GISEL-NEXT: movq $20, %rax
+; X64_GISEL-NEXT: movl $20, %eax
; X64_GISEL-NEXT: addq %rdi, %rax
; X64_GISEL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir
index 33c561f88650..2a5bd6017f38 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir
@@ -136,8 +136,8 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i64_u32
- ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 1879048192
- ; CHECK: $rax = COPY [[MOV64ri32_]]
+ ; CHECK: [[MOV32ri64_:%[0-9]+]]:gr64 = MOV32ri64 1879048192
+ ; CHECK: $rax = COPY [[MOV32ri64_]]
; CHECK: RET 0, implicit $rax
%0(s64) = G_CONSTANT i64 1879048192
$rax = COPY %0(s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ptr-add.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ptr-add.mir
index 2c4a4234e0ca..b8214017a2da 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-ptr-add.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-ptr-add.mir
@@ -23,8 +23,8 @@ body: |
; CHECK-LABEL: name: test_gep_i32
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64_nosp = MOV64ri32 20
- ; CHECK: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri32_]], 0, $noreg
+ ; CHECK: [[MOV32ri64_:%[0-9]+]]:gr64_nosp = MOV32ri64 20
+ ; CHECK: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV32ri64_]], 0, $noreg
; CHECK: $rax = COPY [[LEA64r]]
; CHECK: RET 0, implicit $rax
%0(p0) = COPY $rdi
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