[llvm] 49e4faa - [VE] Support host memory access instructions in MC layer
Simon Moll via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 10 01:02:42 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-06-10T10:02:14+02:00
New Revision: 49e4faa010e1fde152404c1f393a4e8d72f27792
URL: https://github.com/llvm/llvm-project/commit/49e4faa010e1fde152404c1f393a4e8d72f27792
DIFF: https://github.com/llvm/llvm-project/commit/49e4faa010e1fde152404c1f393a4e8d72f27792.diff
LOG: [VE] Support host memory access instructions in MC layer
Summary:
Add LHM/SHM instructions. Add regression tests for them of asmparser,
mccodeemitter, and disassembler. In order to add those instructions,
add new decode functions to disassembler, and add new print functions
to instprinter.
Differential Revision: https://reviews.llvm.org/D81535
Added:
llvm/test/MC/VE/LHM.s
llvm/test/MC/VE/SHM.s
Modified:
llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
llvm/lib/Target/VE/VEInstrFormats.td
llvm/lib/Target/VE/VEInstrInfo.cpp
llvm/lib/Target/VE/VEInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
index 5196d9aa56e7..eecace0d02b1 100644
--- a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
+++ b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
@@ -171,6 +171,10 @@ static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn,
@@ -322,6 +326,30 @@ static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address,
+ const void *Decoder, bool isLoad,
+ DecodeFunc DecodeSX) {
+ unsigned sx = fieldFromInstruction(insn, 48, 7);
+
+ DecodeStatus status;
+ if (isLoad) {
+ status = DecodeSX(MI, sx, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+ }
+
+ status = DecodeAS(MI, insn, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+
+ if (!isLoad) {
+ status = DecodeSX(MI, sx, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+ }
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass);
@@ -352,6 +380,18 @@ static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);
}
+static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder) {
+ return DecodeMemAS(Inst, insn, Address, Decoder, true,
+ DecodeI64RegisterClass);
+}
+
+static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder) {
+ return DecodeMemAS(Inst, insn, Address, Decoder, false,
+ DecodeI64RegisterClass);
+}
+
static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,
const void *Decoder, bool isImmOnly, bool isUImm,
DecodeFunc DecodeSX) {
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
index 38be2b4fa2f8..1fe9423e01b8 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
@@ -181,9 +181,9 @@ void VEInstPrinter::printMemASOperandRRM(const MCInst *MI, int OpNum,
}
}
-void VEInstPrinter::printMemASOperand(const MCInst *MI, int OpNum,
- const MCSubtargetInfo &STI,
- raw_ostream &O, const char *Modifier) {
+void VEInstPrinter::printMemASOperandHM(const MCInst *MI, int OpNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O, const char *Modifier) {
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
printOperand(MI, OpNum, STI, O);
@@ -192,12 +192,15 @@ void VEInstPrinter::printMemASOperand(const MCInst *MI, int OpNum,
return;
}
- const MCOperand &MO = MI->getOperand(OpNum + 1);
- if (!MO.isImm() || MO.getImm() != 0) {
+ if (MI->getOperand(OpNum + 1).isImm() &&
+ MI->getOperand(OpNum + 1).getImm() == 0) {
+ // don't print "+0"
+ } else {
printOperand(MI, OpNum + 1, STI, O);
}
O << "(";
- printOperand(MI, OpNum, STI, O);
+ if (MI->getOperand(OpNum).isReg())
+ printOperand(MI, OpNum, STI, O);
O << ")";
}
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
index 6c1819ec8b14..657cc513b3c5 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
@@ -47,9 +47,9 @@ class VEInstPrinter : public MCInstPrinter {
void printMemASOperandRRM(const MCInst *MI, int OpNum,
const MCSubtargetInfo &STI, raw_ostream &OS,
const char *Modifier = nullptr);
- void printMemASOperand(const MCInst *MI, int OpNum,
- const MCSubtargetInfo &STI, raw_ostream &OS,
- const char *Modifier = nullptr);
+ void printMemASOperandHM(const MCInst *MI, int OpNum,
+ const MCSubtargetInfo &STI, raw_ostream &OS,
+ const char *Modifier = nullptr);
void printMImmOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
raw_ostream &OS);
void printCCOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
diff --git a/llvm/lib/Target/VE/VEInstrFormats.td b/llvm/lib/Target/VE/VEInstrFormats.td
index 60cf1d58b37b..0c02411ff916 100644
--- a/llvm/lib/Target/VE/VEInstrFormats.td
+++ b/llvm/lib/Target/VE/VEInstrFormats.td
@@ -76,6 +76,17 @@ class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,
list<dag> pattern = []>
: RM<opVal, outs, ins, asmstr, pattern>;
+// RRMHM type is to load/store host memory
+// It is similar to RRM and not use sy.
+class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,
+ list<dag> pattern = []>
+ : RRM<opVal, outs, ins, asmstr, pattern> {
+ bits<2> ry = 0;
+ let cy = 0;
+ let sy{6-2} = 0;
+ let sy{1-0} = ry;
+}
+
//-----------------------------------------------------------------------------
// Section 5.3 CF Type
//
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp
index 91fecf00959f..86b2ac2078b1 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -550,15 +550,15 @@ bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const {
.addImm(0)
.addImm(0)
.addImm(0x13b);
- BuildMI(BB, dl, TII.get(VE::SHMri))
+ BuildMI(BB, dl, TII.get(VE::SHMLri))
.addReg(VE::SX61)
.addImm(0)
.addReg(VE::SX63);
- BuildMI(BB, dl, TII.get(VE::SHMri))
+ BuildMI(BB, dl, TII.get(VE::SHMLri))
.addReg(VE::SX61)
.addImm(8)
.addReg(VE::SX8);
- BuildMI(BB, dl, TII.get(VE::SHMri))
+ BuildMI(BB, dl, TII.get(VE::SHMLri))
.addReg(VE::SX61)
.addImm(16)
.addReg(VE::SX11);
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index 5f60e87b1df7..114a6a95220f 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -251,6 +251,7 @@ def CCUIOp : PatLeaf<(cond), [{
}
}]>;
+//===----------------------------------------------------------------------===//
// Addressing modes.
// SX-Aurora has following fields.
// sz: register or 0
@@ -276,7 +277,8 @@ def CCUIOp : PatLeaf<(cond), [{
// AS format:
// MEMriASX, MEMziASX : simple AS format
// MEMriRRM, MEMziRRM : AS format in RRM format
-// well be added later.
+// MEMriHM, MEMziHM : AS format in RRM format for host memory access
+//===----------------------------------------------------------------------===//
// DAG selections for both ASX and AS formats.
def ADDRrri : ComplexPattern<iPTR, 3, "selectADDRrri", [frameindex], []>;
@@ -361,11 +363,21 @@ def MEMziRRM : Operand<iPTR> {
let ParserMatchClass = VEMEMziAsmOperand;
}
-def MEMASri : Operand<iPTR> {
- let PrintMethod = "printMemASOperand";
+// 3. AS HM style assembly instruction format:
+def MEMriHM : Operand<iPTR> {
+ let PrintMethod = "printMemASOperandHM";
let MIOperandInfo = (ops ptr_rc, i32imm);
let ParserMatchClass = VEMEMriAsmOperand;
}
+def MEMziHM : Operand<iPTR> {
+ let PrintMethod = "printMemASOperandHM";
+ let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);
+ let ParserMatchClass = VEMEMziAsmOperand;
+}
+
+//===----------------------------------------------------------------------===//
+// Other operands.
+//===----------------------------------------------------------------------===//
// Branch targets have OtherVT type.
def brtarget32 : Operand<OtherVT> {
@@ -848,6 +860,26 @@ multiclass FIDCRm<string opcStr, bits<8>opc, RegisterClass RC> {
!strconcat(opcStr, " $sx, $sy, $sz")>;
}
+// Multiclass for LHM instruction.
+let mayLoad = 1, hasSideEffects = 0 in
+multiclass LHMm<string opcStr, bits<8> opc, RegisterClass RC> {
+ def ri : RRMHM<opc, (outs RC:$dest), (ins MEMriHM:$addr),
+ !strconcat(opcStr, " $dest, $addr")>;
+ let cz = 0 in
+ def zi : RRMHM<opc, (outs RC:$dest), (ins MEMziHM:$addr),
+ !strconcat(opcStr, " $dest, $addr")>;
+}
+
+// Multiclass for SHM instruction.
+let mayStore = 1, hasSideEffects = 0 in
+multiclass SHMm<string opcStr, bits<8> opc, RegisterClass RC> {
+ def ri : RRMHM<opc, (outs), (ins MEMriHM:$addr, RC:$sx),
+ !strconcat(opcStr, " $sx, $addr")>;
+ let cz = 0 in
+ def zi : RRMHM<opc, (outs), (ins MEMziHM:$addr, RC:$sx),
+ !strconcat(opcStr, " $sx, $addr")>;
+}
+
//===----------------------------------------------------------------------===//
// Instructions
//
@@ -1405,12 +1437,29 @@ defm TSCR : LOADCRm<"tscr", 0x41, I64>;
// Section 8.19.12 - FIDCR (Fetch & Increment/Decrement CR)
defm FIDCR : FIDCRm<"fidcr", 0x51, I64>;
-let cx = 0, cy = 0, cz = 1, hasSideEffects = 0 in {
-let sy = 3 in
-def SHMri : RM<
- 0x31, (outs), (ins MEMASri:$addr, I64:$sx),
- "shm.l $sx, $addr">;
-}
+//-----------------------------------------------------------------------------
+// Section 8.20 - Host Memory Access Instructions
+//-----------------------------------------------------------------------------
+
+// Section 8.20.1 - LHM (Load Host Memory)
+let ry = 3, DecoderMethod = "DecodeLoadASI64" in
+defm LHML : LHMm<"lhm.l", 0x21, I64>;
+let ry = 2, DecoderMethod = "DecodeLoadASI64" in
+defm LHMW : LHMm<"lhm.w", 0x21, I64>;
+let ry = 1, DecoderMethod = "DecodeLoadASI64" in
+defm LHMH : LHMm<"lhm.h", 0x21, I64>;
+let ry = 0, DecoderMethod = "DecodeLoadASI64" in
+defm LHMB : LHMm<"lhm.b", 0x21, I64>;
+
+// Section 8.20.2 - SHM (Store Host Memory)
+let ry = 3, DecoderMethod = "DecodeStoreASI64" in
+defm SHML : SHMm<"shm.l", 0x31, I64>;
+let ry = 2, DecoderMethod = "DecodeStoreASI64" in
+defm SHMW : SHMm<"shm.w", 0x31, I64>;
+let ry = 1, DecoderMethod = "DecodeStoreASI64" in
+defm SHMH : SHMm<"shm.h", 0x31, I64>;
+let ry = 0, DecoderMethod = "DecodeStoreASI64" in
+defm SHMB : SHMm<"shm.b", 0x31, I64>;
//===----------------------------------------------------------------------===//
// Instructions for CodeGenOnly
diff --git a/llvm/test/MC/VE/LHM.s b/llvm/test/MC/VE/LHM.s
new file mode 100644
index 000000000000..5ed41a3e8130
--- /dev/null
+++ b/llvm/test/MC/VE/LHM.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: lhm.l %s20, 20(%s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x03,0x14,0x21]
+lhm.l %s20, 20(%s11)
+
+# CHECK-INST: lhm.w %s20, 8192()
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x02,0x14,0x21]
+lhm.w %s20, 8192()
+
+# CHECK-INST: lhm.h %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x01,0x14,0x21]
+lhm.h %s20, (%s11)
+
+# CHECK-INST: lhm.b %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x00,0x14,0x21]
+lhm.b %s20, %s11
diff --git a/llvm/test/MC/VE/SHM.s b/llvm/test/MC/VE/SHM.s
new file mode 100644
index 000000000000..9eab46b7a7a8
--- /dev/null
+++ b/llvm/test/MC/VE/SHM.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: shm.l %s20, 20(%s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x03,0x14,0x31]
+shm.l %s20, 20(%s11)
+
+# CHECK-INST: shm.w %s20, 8192()
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x02,0x14,0x31]
+shm.w %s20, 8192()
+
+# CHECK-INST: shm.h %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x01,0x14,0x31]
+shm.h %s20, (%s11)
+
+# CHECK-INST: shm.b %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x00,0x14,0x31]
+shm.b %s20, %s11
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