[PATCH] D81440: [VE] Support Transfer Control Instructions in MC layer

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka.
kaz7 added projects: LLVM, VE.
Herald added subscribers: llvm-commits, jfb, hiraditya.

Add regression tests of asmparser, mccodeemitter, and disassembler for
transfer control instructions.  Add FENCEI/FENCEM/FENCEC/SVOB instructions
also.  Add new instruction format to represent FENCE* instructions too.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81440

Files:
  llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
  llvm/lib/Target/VE/VEInstrFormats.td
  llvm/lib/Target/VE/VEInstrInfo.td
  llvm/test/MC/VE/FENCE.s
  llvm/test/MC/VE/SVOB.s

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