[PATCH] D81045: [MLIR] Modify HasParent trait to allow one of several op's as a parent

Jacques Pienaar via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 8 11:35:29 PDT 2020


jpienaar added inline comments.


================
Comment at: llvm/include/llvm/Support/Casting.h:147
+template <typename First, typename... Rest, typename Y>
+LLVM_NODISCARD inline typename std::enable_if<sizeof...(Rest) != 0, bool>::type
+isa(const Y &Val) {
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I'm worried that folks may not notice this change based on the change description (e.g., the change sounds MLIR specific), could you make this a separate change? (just focused on isa changes)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81045/new/

https://reviews.llvm.org/D81045





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