[PATCH] D81275: [AMDGPU] Move default initialization of M0 register after the instruction selection

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Overall this is probably fine to move. FYI I was hoping to move in a different direction for m0 initialization, where we would stop reserving it and use ordinary copies to initialize it. This would allow us to move/eliminate the custom M0 init optimizations.

Can this remove the SI_INIT_M0 instruction now?



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Comment at: llvm/lib/Target/AMDGPU/DSInstructions.td:55
+  // initialize M0 in SITargetLowering::AdjustInstrPostInstrSelection
+  let hasPostISelHook = has_m0_read;
 }
----------------
Could you just set hasPostISelHook to 0 for the special cases?


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10790
 
+// these instructions specify M0 value during selection,
+// see AMDGPUDAGToDAGISel::glueCopyToM0, SITargetLowering::copyToM0 usage
----------------
Capitalize


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10792
+// see AMDGPUDAGToDAGISel::glueCopyToM0, SITargetLowering::copyToM0 usage
+static bool hasNonDefaultM0(unsigned Opcode) {
+  switch(Opcode) {
----------------
You could just use this in an assert if you disabled the post isel hook for the special cases


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10821-10822
+static void initDefaultM0(MachineInstr &MI) {
+  if (!MI.getNumMemOperands())
+    return;
+
----------------
Should not rely on the memory operands. isDS() would be more reliable 


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10825
+  MachineFunction &MF = *MI.getParent()->getParent();
+  auto &Subtarget = static_cast<const GCNSubtarget&>(MF.getSubtarget());
+  auto AS = (*MI.memoperands_begin())->getAddrSpace();
----------------
Make a member function of SITargetLowering and avoid the need to find Subtarget etc.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10828
+  unsigned M0Init;
+  if (AS == AMDGPUAS::REGION_ADDRESS)
+    M0Init = MF.getInfo<SIMachineFunctionInfo>()->getGDSSize();
----------------
Check the GDS bit


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10851
 
+  initDefaultM0(MI);
+
----------------
TII->isDS()?


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  https://reviews.llvm.org/D81275/new/

https://reviews.llvm.org/D81275