[PATCH] D80922: GlobalISel: Infer nofpexcept flag during selection for non-strict ops

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 1 06:23:44 PDT 2020


arsenm created this revision.
arsenm added reviewers: paquette, aemerson, aditya_nandakumar, dsanders.
Herald added subscribers: kerbowa, rovka, nhaehnle, wdng, jvesely.
Herald added a project: LLVM.

Match SelectionDAG's behavior of adding nofpexcept to out instructions
that may raise fp exceptions that are selected from instructions that
do not.


https://reviews.llvm.org/D80922

Files:
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
  llvm/test/CodeGen/X86/GlobalISel/select-add.mir
  llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
  llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
  llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
  llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
  llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir
  llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
  llvm/test/CodeGen/X86/GlobalISel/select-sub.mir
  llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir
  llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D80922.267595.patch
Type: text/x-patch
Size: 238052 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200601/8b84208f/attachment-0001.bin>


More information about the llvm-commits mailing list