[PATCH] D80885: [VectorCombine] scalarizeBinop - support an all-constant src vector operand

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

Code looks good, but let's pre-commit some changes to the tests to exercise the cost model.

1. It's mostly <2 x i64> or <2 x double> - can we create a a negative test or show an SSE vs AVX diff by changing types?
2. Throw in some extra uses and see if that makes cost changes that inhibit the transform.



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Comment at: llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll:684
+
+define <4 x i32> @PR42174(<4 x i32> %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8) {
+; CHECK-LABEL: @PR42174(
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RKSimon wrote:
> Do we need this or can we just rely on the phaseordering test?
I don't see any value in duplicating this test. We'll know if anything breaks meaningfully from the PhaseOrdering version of the test.


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https://reviews.llvm.org/D80885