[PATCH] D80906: [DAG] SimplifyDemandedVectorElts Bugfix for X86ISD::VBROADCAST calculating wrong DemandedElts for its Operand

[Bing Yu via Phabricator via llvm-commits]

yubing created this revision.
yubing added reviewers: RKSimon, LuoYuanke, pengfei.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.
yubing edited the summary of this revision.

Assume we have:
t60: v4i32 = insert_vector_elt t29, t27, Constant:i64<2>
t63: v8i32 = X86ISD::VBROADCAST t60
if t60's DemandElts is 0b10110001, t63's DemandElts should be 0b1011 | 0b0001 = 0b1011, but current code will set t63's DemandElts to 0b0001

Simon, it seems very difficult to write a testcase, , do you have any  suggestions for the testcase?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80906

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36843,6 +36843,7 @@
     MVT SrcVT = Src.getSimpleValueType();
     if (!SrcVT.isVector())
       return false;
+    int SrcNumElts = SrcVT.getVectorNumElements();
     // Don't bother broadcasting if we just need the 0'th element.
     if (DemandedElts == 1) {
       if (Src.getValueType() != VT)
@@ -36851,7 +36852,12 @@
       return TLO.CombineTo(Op, Src);
     }
     APInt SrcUndef, SrcZero;
-    APInt SrcElts = APInt::getOneBitSet(SrcVT.getVectorNumElements(), 0);
+    APInt SrcElts(SrcNumElts, 0);
+    for (int Idx = 0; Idx < NumElts; Idx++) {
+      if (!DemandedElts[Idx])
+        continue;
+      SrcElts.setBit(Idx % SrcNumElts);
+    }
     if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO,
                                    Depth + 1))
       return true;


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