[PATCH] D77152: [SelectionDAG] Better legalization for FSHL and FSHR

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D77152#2060878 <https://reviews.llvm.org/D77152#2060878>, @nemanjai wrote:

> In D77152#2057762 <https://reviews.llvm.org/D77152#2057762>, @RKSimon wrote:
>
> > IIRC powerpc scalar shift ops can use shift amounts upto the bitwidth (not bitwidth-1) so there might be custom funnel shifts that they can do with that - @hfinkel @nemanjai any thoughts?
>
>
> The reg+reg shifts consider enough bits of the register that contains the shift amount to shift by `bitwidth * 2 - 1` bits. For example `(i64:x << y) == 0 for 64 <= y < 128`. The immediate forms do not have this property (i.e. there is no way to encode `(i64:x << 64)` since the immediate field is 6 bits.
>  But even for the reg+reg versions, I can't think of how we can utilize this.


That's perfect. It means that for e.q. the fshl_i32 test case, the original code is fine and we don't even need the iseleq to handle the shift-by-zero case:

  ; CHECK-NEXT:    andi. 5, 5, 31
  ; CHECK-NEXT:    subfic 6, 5, 32
  ; CHECK-NEXT:    slw 5, 3, 5
  ; CHECK-NEXT:    srw 4, 4, 6
  ; CHECK-NEXT:    or 4, 5, 4
  ; CHECK-NEXT:    iseleq 3, 3, 4 # not needed!

Unfortunately I think we'd need a PowerPC-specific lowering to implement this. (It doesn't matter about the immediate forms because funnel shifts by immediate-0 can be folded away.)


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