[llvm] 1a9e0d7 - AMDGPU: Make S_DENORM_MODE not be a scheduling boundary

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-05-28T10:39:33-04:00
New Revision: 1a9e0d7092145e33175f628f4cdd28acf0d17100

URL: https://github.com/llvm/llvm-project/commit/1a9e0d7092145e33175f628f4cdd28acf0d17100
DIFF: https://github.com/llvm/llvm-project/commit/1a9e0d7092145e33175f628f4cdd28acf0d17100.diff

LOG: AMDGPU: Make S_DENORM_MODE not be a scheduling boundary

Now that the mode register uses/defs should be properly modeled, we
don't need to treat the FP mode switch as an arbitrary side effect.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    llvm/lib/Target/AMDGPU/SIInstrInfo.td
    llvm/lib/Target/AMDGPU/SOPInstructions.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index e68f8a95efed..0300de69caea 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2944,10 +2944,12 @@ bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
   // Target-independent instructions do not have an implicit-use of EXEC, even
   // when they operate on VGPRs. Treating EXEC modifications as scheduling
   // boundaries prevents incorrect movements of such instructions.
+
+  // TODO: Don't treat setreg with known constant that only changes MODE as
+  // barrier.
   return MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
          MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
          MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
-         MI.getOpcode() == AMDGPU::S_DENORM_MODE ||
          changesVGPRIndexingMode(MI);
 }
 

diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index b988de596c64..62b7f8318fd0 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -264,7 +264,7 @@ def SIload_d16_hi_i8 : SDNode<"AMDGPUISD::LOAD_D16_HI_I8",
 
 def SIdenorm_mode : SDNode<"AMDGPUISD::DENORM_MODE",
   SDTypeProfile<0 ,1, [SDTCisInt<0>]>,
-  [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]
+  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
 >;
 
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 4f9aaa1bc604..7b8c2c27b806 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1218,8 +1218,7 @@ let SubtargetPredicate = isGFX10Plus in {
   def S_WAITCNT_DEPCTR :
     SOPP <0x023, (ins s16imm:$simm16), "s_waitcnt_depctr $simm16">;
 
-  let hasSideEffects = 1, Uses = [MODE], Defs = [MODE] in {
-    // FIXME: Should remove hasSideEffects
+  let hasSideEffects = 0, Uses = [MODE], Defs = [MODE] in {
     def S_ROUND_MODE :
       SOPP<0x024, (ins s16imm:$simm16), "s_round_mode $simm16">;
     def S_DENORM_MODE :