[PATCH] D80175: [PowerPC][MachineCombiner] reassociate fma to expose more ILP

[ChenZheng via Phabricator via llvm-commits]

shchenz added a comment.

@spatel , Thanks for reminding the compiling time issue. I will have a test about compiling time later.

This was the prototype I implemented in DAGCombiner,

Before the final `return` statement of `visitFMA()` function in file `DAGCombiner.cpp`

Sorry for the bad formatting and it is not well tested.

  +
  +  // expose more ILP:
  +  // (fma E, F, (fma C, D, (add A, B))) -> add ((fma C, D, A), (fma E, F, A))
  +  TargetSchedModel SchedModel;
  +  SchedModel.init(&DAG.getSubtarget());
  +  if (UnsafeFPMath && SchedModel.getIssueWidth() > 1 && N2.getOpcode() == ISD::FMA && N2.hasOneUse() && (Options.UnsafeFPMath || isContractable(N2.getNode()))) {
  +    SDValue OpADD = N2.getOperand(2);
  +    if (OpADD.getOpcode() == ISD::FADD && OpADD.hasOneUse()) {
  +      SDValue ADDLHS = DAG.getNode(ISD::FMA, SDLoc(N2), VT, N2.getOperand(0), N2.getOperand(1), OpADD.getOperand(0), Flags);
  +      SDValue ADDRHS = DAG.getNode(ISD::FMA, SDLoc(N2), VT, N0, N1, OpADD.getOperand(1), Flags);
  +      return DAG.getNode(ISD::FADD, DL, VT, ADDLHS, ADDRHS, OpADD.getNode()->getFlags());
  +    }
  +  }
  +


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  https://reviews.llvm.org/D80175/new/

https://reviews.llvm.org/D80175