[PATCH] D80720: [CodeGen,AArch64] Fix up warnings in splitStores

[David Sherwood via Phabricator via llvm-commits]

david-arm created this revision.
david-arm added a reviewer: sdesmalen.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

The code for trying to split up stores is designed for NEON vectors,
where we support arbitrary alignments. However, for SVE all vectors
should be aligned to 16 bytes anyway so we may as well bail out
early.

This change fixes up remaining warnings in a couple of tests so
I have added checks to make sure no warnings appear.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80720

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-callbyref-notailcall.ll
  llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll


Index: llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
+++ llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
@@ -1,4 +1,6 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s 2>&1 | FileCheck %s
+
+; CHECK-NOT: warning
 
 ; Test that z8 and z9, passed in by reference, are correctly loaded from x0 and x1.
 ; i.e. z0 =  %z0
Index: llvm/test/CodeGen/AArch64/sve-callbyref-notailcall.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-callbyref-notailcall.ll
+++ llvm/test/CodeGen/AArch64/sve-callbyref-notailcall.ll
@@ -1,6 +1,8 @@
 ; Because some arguments are passed by reference (through stack),
 ; the compiler should not do tail-call optimization.
-; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+sve < %s 2>&1 | FileCheck %s
+
+; CHECK-NOT: warning
 
 ; CHECK-LABEL: caller:
 ; CHECK:       addvl sp, sp, #-[[STACKSIZE:[0-9]+]]
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -12035,7 +12035,8 @@
 
   SDValue StVal = S->getValue();
   EVT VT = StVal.getValueType();
-  if (!VT.isVector())
+  // All SVE vectors should be aligned to 16 bytes
+  if (!VT.isVector() || VT.isScalableVector())
     return SDValue();
 
   // If we get a splat of zeros, convert this vector store to a store of


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