[PATCH] D80690: [RISCV] Support libunwind for riscv32

[kamlesh kumar via Phabricator via llvm-commits]

kamleshbhalui marked an inline comment as done.
kamleshbhalui added inline comments.


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Comment at: libunwind/include/__libunwind_config.h:132
 #    define _LIBUNWIND_TARGET_RISCV 1
-#    define _LIBUNWIND_CONTEXT_SIZE 64
+#    define _LIBUNWIND_CONTEXT_SIZE (32 * (__riscv_xlen + __riscv_flen) / 64)
 #    define _LIBUNWIND_CURSOR_SIZE 76
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luismarques wrote:
> This doesn't seem correct.
OK so it appears that in principle we could have 4 combinations 

ILP32 + "f" : xlen = 32, flen = 32
ILP32 + "fd" : xlen = 32, flen = 64
LP64 + "f" : xlen = 64, flen = 32
LP64 + "fd" : xlen = 64, flen = 64

So instead of having fixed size area for each kind of register thought of having packed size.
please point me where it can cause problem?




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https://reviews.llvm.org/D80690